Re: [PATCH DNM v3 8/8] arm64: dts: qcom: kaanapali: Add MPAM MSC nodes for the L2 caches

[Yin Li]

On 10/12/2026 7:27 PM, Ben Horgan wrote:
> Hi Yin,
>
> On 12/10/2026 11:48, Yin Li wrote:
> > On 10/9/2026 5:00 AM, Rob Herring wrote:
> > > On Thu, Oct 08, 2026 at 02:41:17PM +0800, Yin Li wrote:
> > > > Add an MPAM MSC device node for each L2 cache. Each MSC is nested
> > > > directly under its L2 cache node so that the cache node is the MSC's
> > > > parent device and its CPU affinity is derived from that cache.
> > > >
> > > > The L2 cache nodes are placed directly under the root node. The root is
> > > > the root of the physical address space, so each cache node only needs an
> > > > identity 'ranges' property for its nested MSC's 'reg' to be resolved to
> > > > a physical address. The two caches use distinct node names (l2-cache-0
> > > > and l2-cache-1) since a cache node has no MMIO unit-address of its own.
> > > >
> > > > The nodes are disabled by default. Production firmware does not expose
> > > > MSC register access to the OS, so these nodes can only be enabled on a
> > > > local test setup where firmware permits direct MMIO access to the MSCs.
> > > > This DTS is therefore only an example for other platform DT authors and
> > > > is not intended to be merged.
> > > >
> > > > Co-developed-by: Huang Yiwei <huang.yiwei@xxxxxxxxxxxxxxxx>
> > > > Signed-off-by: Huang Yiwei <huang.yiwei@xxxxxxxxxxxxxxxx>
> > > > Signed-off-by: Yin Li <yin.li@xxxxxxxxxxxxxxxx>
> > > > ---
> > > >    arch/arm64/boot/dts/qcom/kaanapali.dtsi | 50 +++++++++++++++++++++++++--------
> > > >    1 file changed, 38 insertions(+), 12 deletions(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> > > > index 131fd2a16c54..b1dcb1e9c570 100644
> > > > --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> > > > +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>
> [...]
>
> > > > +
> > > > +        msc@19870000 {
> > > > +            compatible = "arm,mpam-msc";
> > > > +            reg = <0x0 0x19870000 0x0 0x10000>;
> > >
> > > The MPAM register length is 0x321C.
> >
> > You are right, the MPAM register space is 0x321c per the specification.
> > Will update accordingly.
>
> That is the full extent but truncation is allowed by the architecture.
>
> Section B.9 9.2.3 Permitted truncation of an MPAM feature page IQGXFF it mentions
> some conditions but these haven't been updated for the introduction of FEAT_MPAM_MSC_DOMAINS.
>
> Does your implementation have domains?

Hi Ben,

Our implementation does not have domains. So 0x321c reflects the full 
feature page for MSC.

Thanks,
Yin


> Thanks,
>
> Ben
>
>
> > Thanks,
> > Yin
> >
> > > Rob

--
Thx and BRs,
Yin