Re: [PATCH v2 8/8] iio: adc: rzt2h: Add support for RZ/V2H(P) SoC
From: Lad, Prabhakar
Date: Tue Oct 13 2026 - 08:53:08 EST
Hi Biju,
On Mon, Oct 12, 2026 at 7:36 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@xxxxxxxxx>
> > Sent: 09 October 2026 19:41
> > Subject: [PATCH v2 8/8] iio: adc: rzt2h: Add support for RZ/V2H(P) SoC
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Add support for the ADC found on the Renesas RZ/V2H(P) SoC, which shares the RZ/T2H ADC IP but differs in
> > channel count, sampling, calibration and resolution support.
> >
> > The RZ/V2H(P) ADC provides 8 channels, has a fixed conversion time of
> > 20 ADCLK cycles, does not support calibration, and supports selectable 12-bit and 8-bit conversion
> > resolution.
> >
> > Expose the fixed sampling frequency as a read-only attribute and allow the conversion resolution to be
> > changed through the scale attribute.
> > Use extended scan types so the reported scan type follows the selected resolution, and prevent resolution
> > changes while buffered capture is active.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > ---
> > v1->v2:
> > - Updated Kconfig description
> > - Included array_size.h
> > - Dropped unnecessary extra line in rzt2h_adc_write_scale
> > ---
> > drivers/iio/adc/Kconfig | 10 +-
> > drivers/iio/adc/rzt2h_adc.c | 201 +++++++++++++++++++++++++++++++++++-
> > 2 files changed, 205 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index a802d8ee4dd9..9a58f8b5868b 100644
> > --- a/drivers/iio/adc/Kconfig
> > +++ b/drivers/iio/adc/Kconfig
> > @@ -1587,14 +1587,18 @@ config RZN1_ADC
> > module will be called rzn1-adc.
> >
> > config RZT2H_ADC
> > - tristate "Renesas RZ/T2H / RZ/N2H ADC driver"
> > + tristate "Renesas RZ/T2H / RZ/N2H (and similar SoCs) ADC driver"
> > depends on ARCH_RENESAS || COMPILE_TEST
> > select IIO_ADC_HELPER
> > select IIO_BUFFER
> > select IIO_KFIFO_BUF
> > + select POWER_SEQUENCING
> > help
> > - Say yes here to build support for the ADC found in Renesas
> > - RZ/T2H / RZ/N2H SoCs.
> > + Say yes here to build support for the ADC found in Renesas SoCs:
> > + - RZ/N2H
> > + - RZ/T2H
> > + - RZ/V2H(P)
> > + - RZ/V2N
> >
> > To compile this driver as a module, choose M here: the
> > module will be called rzt2h_adc.
> > diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c index 0703c2025e3f..be8273f3b61d
> > 100644
<snip>
> > static const struct rzt2h_adc_chip_info rzt2h_adc_info = {
> > .chan_template = &rzt2h_adc_chan_template,
> > .sst_to_freq = rzt2h_adc_sst_to_freq,
> > @@ -796,6 +973,7 @@ static const struct rzt2h_adc_chip_info rzt2h_adc_info = { };
> >
> > static const struct of_device_id rzt2h_adc_match[] = {
> > + { .compatible = "renesas,r9a09g057-adc", .data = &rzv2h_adc_info },
> > { .compatible = "renesas,r9a09g077-adc", .data = &rzt2h_adc_info },
> > { }
> > };
> > @@ -804,8 +982,17 @@ MODULE_DEVICE_TABLE(of, rzt2h_adc_match); static int
> > rzt2h_adc_pm_runtime_suspend(struct device *dev) {
> > struct rzt2h_adc *adc = dev_get_drvdata(dev);
> > + int ret;
> > +
> > + ret = pwrseq_disable(adc->pwrseq);
> > + if (ret)
> > + return ret;
> > +
> > + ret = reset_control_assert(adc->rstc);
>
> I guess to apply assert reset, IP needs power.
> So, you need to asset first and then power off.
>
The HW manual doesn't mention any ordering of power and reset,
although it does mention the ordering of power and clock which the
current code adheres to. For example see the below logs where register
RZT2H_ADANSA0_REG is written a value of 0x56 at the begining of the
suspend call and the same register is read back in the suspend call
after turning off the power and in the resume path the same register
is read back at the very end and we can see the value of this register
is reported as 0x0 which is expected to reset to its initial value
(full log can be seen here
https://gist.github.com/prabhakarlad/def672bbca9cc51d0398a6549bcf1b80).
Please let me know if I have misunderstood something here.
Logs:
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
rzv2h-evk login: root
WARNING: Poky is a reference Yocto Project distribution that should be used for
testing and development purposes only. It is recommended that you create your
own distribution for production use.
root@rzv2h-evk:~# >>>>>>>>> First Cycle <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
root@rzv2h-evk:~# cat /sys/bus/iio/devices/iio\:device0/in_voltage0_raw
[ 46.125340] rzv2h-cpg 10420000.clock-controller: CLK_ON 0x640/adc_0_adclk on
[ 46.132399] rzv2h-cpg 10420000.clock-controller: CLK_ON 0x640/adc_0_pclk on
[ 46.139386] Resuming ADC
[ 46.141915] rzv2h-cpg 10420000.clock-controller: deassert id:110 offset:0x93c
[ 46.149054] Enabling ADC pwrseq
[ 46.152245] ADANSA0_REG: 0x0 in resume
216
root@rzv2h-evk:~# [ 46.531171] Suspending ADC
[ 46.533951] ADANSA0_REG: 0x56 before power down
[ 46.538732] Disabling ADC pwrseq
[ 46.542095] ADANSA0_REG: 0x56 after power down
[ 46.546681] rzv2h-cpg 10420000.clock-controller: assert id:110 offset:0x93c
[ 46.553829] rzv2h-cpg 10420000.clock-controller: CLK_ON 0x640/adc_0_pclk off
[ 46.560951] rzv2h-cpg 10420000.clock-controller: CLK_ON 0x640/adc_0_adclk off
root@rzv2h-evk:~# ->>>>>>>>> Second Cycle <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
root@rzv2h-evk:~# cat /sys/bus/iio/devices/iio\:device0/in_voltage0_raw
[ 50.491213] rzv2h-cpg 10420000.clock-controller: CLK_ON 0x640/adc_0_adclk on
[ 50.498271] rzv2h-cpg 10420000.clock-controller: CLK_ON 0x640/adc_0_pclk on
[ 50.505242] Resuming ADC
[ 50.507785] rzv2h-cpg 10420000.clock-controller: deassert id:110 offset:0x93c
[ 50.514923] Enabling ADC pwrseq
[ 50.518111] ADANSA0_REG: 0x0 in resume
126
root@rzv2h-evk:~# [ 50.896990] Suspending ADC
[ 50.899881] ADANSA0_REG: 0x56 before power down
[ 50.904545] Disabling ADC pwrseq
[ 50.907914] ADANSA0_REG: 0x56 after power down
[ 50.912504] rzv2h-cpg 10420000.clock-controller: assert id:110 offset:0x93c
[ 50.919642] rzv2h-cpg 10420000.clock-controller: CLK_ON 0x640/adc_0_pclk off
[ 50.926761] rzv2h-cpg 10420000.clock-controller: CLK_ON 0x640/adc_0_adclk off
root@rzv2h-evk:~#
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
Changes made to generate the above logs:
--------------------------------------------------
diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 7ce94680c79a..eab6237dca4c 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -1169,7 +1169,7 @@ static int rzv2h_mod_clock_endisable(struct
clk_hw *hw, bool enable)
u32 value;
int error;
- dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,
+ dev_err(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,
str_on_off(enable));
if (enabled == enable)
@@ -1324,7 +1324,7 @@ static int __rzv2h_cpg_assert(struct
reset_controller_dev *rcdev,
u32 mon;
int ret;
- dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n",
+ dev_err(rcdev->dev, "%s id:%ld offset:0x%x\n",
assert ? "assert" : "deassert", id, reg);
if (!assert)
diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c
index be8273f3b61d..36ff6da87138 100644
--- a/drivers/iio/adc/rzt2h_adc.c
+++ b/drivers/iio/adc/rzt2h_adc.c
@@ -984,9 +984,14 @@ static int rzt2h_adc_pm_runtime_suspend(struct device *dev)
struct rzt2h_adc *adc = dev_get_drvdata(dev);
int ret;
+ pr_err("Suspending ADC\n");
+
+ writew(0x56, adc->base + RZT2H_ADANSA0_REG);
+ pr_err("ADANSA0_REG: 0x%x before power down\n",
readw(adc->base + RZT2H_ADANSA0_REG));
ret = pwrseq_disable(adc->pwrseq);
if (ret)
return ret;
+ pr_err("ADANSA0_REG: 0x%x after power down\n", readw(adc->base
+ RZT2H_ADANSA0_REG));
ret = reset_control_assert(adc->rstc);
if (ret)
@@ -1001,6 +1006,8 @@ static int rzt2h_adc_pm_runtime_resume(struct device *dev)
const struct rzt2h_adc_chip_info *chip_info = adc->chip_info;
int ret;
+ pr_err("Resuming ADC\n");
+
ret = reset_control_deassert(adc->rstc);
if (ret)
return ret;
@@ -1011,6 +1018,8 @@ static int rzt2h_adc_pm_runtime_resume(struct device *dev)
return ret;
}
+ pr_err("ADANSA0_REG: 0x%x in resume\n", readw(adc->base +
RZT2H_ADANSA0_REG));
+
if (!(chip_info->features & RZT2H_ADC_FEATURE_CALIBRATION))
return 0;
diff --git a/drivers/power/sequencing/pwrseq-renesas-pwrrdy.c
b/drivers/power/sequencing/pwrseq-renesas-pwrrdy.c
index 40760977f7de..b6886dba92a9 100644
--- a/drivers/power/sequencing/pwrseq-renesas-pwrrdy.c
+++ b/drivers/power/sequencing/pwrseq-renesas-pwrrdy.c
@@ -8,6 +8,7 @@
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/pwrseq/consumer.h>
#include <linux/pwrseq/provider.h>
#include <linux/regmap.h>
@@ -31,6 +32,7 @@ static int pwrseq_rzv2h_adc_enable(struct
pwrseq_device *pwrseq)
struct regmap *regmap = pwrseq_device_get_drvdata(pwrseq);
int ret;
+ pr_err("Enabling ADC pwrseq\n");
ret = regmap_clear_bits(regmap, RZV2H_SYS_ADC_CFG,
RZV2H_SYS_ADC_CFG_SY_MSTP_ADA);
if (ret)
@@ -45,6 +47,7 @@ static int pwrseq_rzv2h_adc_disable(struct
pwrseq_device *pwrseq)
{
struct regmap *regmap = pwrseq_device_get_drvdata(pwrseq);
+ pr_err("Disabling ADC pwrseq\n");
return regmap_set_bits(regmap, RZV2H_SYS_ADC_CFG,
RZV2H_SYS_ADC_CFG_SY_MSTP_ADA);
}
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Cheers,
Prabhakar