Re: [PATCH v2 2/8] iio: adc: rzt2h: Wait for the analog part to stop after a forced stop

[Andy Shevchenko]

On Fri, Oct 09, 2026 at 07:41:16PM +0100, Prabhakar wrote:

> When ADCSR.ADST is cleared to forcibly stop a conversion, the analog part
> of the A/D converter can take up to 2 ADCLK cycles to stop operating.
> 
> Wait for the write to ADCSR to complete and allow the analog part to stop
> before reconfiguring or restarting the converter.

...

> +	/*
> +	 * When a conversion is forcibly stopped, the analog part of the A/D
> +	 * converter takes up to 2 ADCLK cycles to stop operating. Read back
> +	 * ADCSR to make sure the write has reached the hardware before
> +	 * starting the delay.
> +	 */
> +	readw(adc->base + RZT2H_ADCSR_REG);
> +	ndelay(DIV_ROUND_UP(RZT2H_ADC_STOP_CYCLES * NSEC_PER_SEC,
> +			    adc->adclk_rate));

A single line (84 characters) is okay in this case.

	ndelay(DIV_ROUND_UP(RZT2H_ADC_STOP_CYCLES * NSEC_PER_SEC, adc->adclk_rate));

-- 
With Best Regards,
Andy Shevchenko