Re: [PATCH v6 3/3] ARM: dts: renesas: r9a06g032: add EDAC node

[Paul Louvel]

On Tue Oct 13, 2026 at 3:52 PM CEST, Miquel Raynal wrote:
>
>>>> +               edac: memory-controller@4000d000 {
>>>> +                       compatible = "renesas,r9a06g032-ddr-edac", "cdns,ddr-edac";
>>>> +                       reg = <0x4000d000 0x1000>;
>>>> +                       interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                       clocks = <&sysctrl R9A06G032_CLK_DDRC>, <&sysctrl R9A06G032_HCLK_DDRC>;
>>>> +                       clock-names = "ddrc", "pclk";
>>>> +                       status = "disabled";
>>>
>>> Should this node be enabled by default, or am I too naive?
>>
>> The bootloader will be responsible to initialize the DDR controller and enable
>> ECC if specified. On this specific platform (r9a06g032), ECC is disabled by
>> default.
>> Enabling the ECC require a specific property to be present under the controller
>> node in U-Boot. I think it make sense to keep it by default disabled.
>
> Wouldn't enabling it also require some reserved memory regions? There
> should be an impact on the amount of available RAM for the system.

Yes, if the memory controller is configured by the bootloader to enable ECC.
U-Boot would fixup the memory node to reflect the correct amount of available
RAM in this case.

At the Linux level, it would not change anything if the EDAC driver is probed by
and ECC is disabled. It would just simply inform the EDAC core that SECDEC is
not supported and that's it.

>
> Thanks,
> Miquèl

-- 
Paul Louvel, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com