[PATCH] phy: rockchip: naneng-combphy: Fix overwritten PLL SSC control bit

[Shawn Lin]

rk_combphy_common_cfg_ssc() first sets RK3568_PHYREG33_PLL_SSC_CTRL on the
RK3588 and RK3576 SoCs, then, for PCIe at 24MHz, programs the PLL KVCO
adjust field. The latter used a plain writel() of the FIELD_PREP() value,
which cleared all the other bits of RK3568_PHYREG33, including the
PLL_SSC_CTRL bit that had just been set a few lines above.

Use rockchip_combphy_updatel() so that only the KVCO field is updated and
the SSC control bit is preserved, as the comment and the pre-consolidation
code intended.

Fixes: 0b31f297557f ("phy: rockchip: naneng-combphy: Consolidate SSC configuration")
Signed-off-by: Shawn Lin <shawn.lin@xxxxxxxxxxxxxx>
---

 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 3102a99..b6cc010 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -526,7 +526,8 @@ static void rk_combphy_common_cfg_ssc(struct rockchip_combphy_priv *priv, unsign
 
 		val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
 				 RK3576_PHYREG33_PLL_KVCO_VALUE);
-		writel(val, priv->mmio + RK3568_PHYREG33);
+		rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
+					 val, RK3568_PHYREG33);
 	}
 }
 
-- 
2.7.4