[PATCH 2/4] clk: ti: fapll: Fix clock speed calculation

[Ettore Chimenti]

From: Andrew Goodbody <andrew.goodbody@xxxxxxxxxx>

The fractional part of the divider was being treated as 1/10000000 wheras
it is in fact 1/16777215. This led to incorrect clock speeds being
reported when a fractional divider was in use. Correct it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@xxxxxxxxxx>
Signed-off-by: Ettore Chimenti <ettore.chimenti@xxxxxxxxxx>
---
 drivers/clk/ti/fapll.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index ae2f6fed10f6..008a61f45ac1 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -336,8 +336,8 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
 		v = readl_relaxed(synth->freq);
 		synth_int_div = (v >> 24) & 0xf;
 		synth_frac_div = v & 0xffffff;
-		synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
-		rate *= 10000000;
+		synth_div_freq = (synth_int_div * 16777215) + synth_frac_div;
+		rate *= 16777215;
 		do_div(rate, synth_div_freq);
 		rate *= SYNTH_PHASE_K;
 	}

-- 
2.56.0