Re: [PATCH v7 06/15] perf annotate-arm64: Support store instruction tracking

[Tengda Wu]

On 2026/10/16 7:02, Namhyung Kim wrote:
> On Tue, Oct 13, 2026 at 01:28:04PM +0000, Tengda Wu wrote:
>> Extend update_insn_state_arm64() to handle standard store instructions
>> (str, stur, stlr, stp). Exclusive stores (e.g., stxr, stxp) are omitted
>> as they exhibit different operand semantics.
>>
>> Unlike load instructions, a store instruction sets a value in the struct
>> within the memory where the destination register resides, and does not
>> alter its type. Therefore, no processing is required for the transfer.
> 
> But the target location also can be stack which requires type info,
> right?  Oh, I think you have a patch later to handle that.

Yes, this is supported in the subsequent patch 10 for stack-related loads
and stores.

Thanks,
Tengda

> 
> Thanks,
> Namhyung
> >>
>> The only point to note is that store instructions support pre-index and
>> post-index addressing modes, so calling adjust_reg_index_state() is still
>> necessary to handle their addressing.
>>
>> Reviewed-by: Ian Rogers <irogers@xxxxxxxxxx>
>> Signed-off-by: Tengda Wu <wutengda@xxxxxxxxxxxxxxx>
>> ---
>>  .../perf/util/annotate-arch/annotate-arm64.c  | 25 +++++++++++++++++++
>>  1 file changed, 25 insertions(+)
>>
>> diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/util/annotate-arch/annotate-arm64.c
>> index fb48bf95b32f..54d9928b536f 100644
>> --- a/tools/perf/util/annotate-arch/annotate-arm64.c
>> +++ b/tools/perf/util/annotate-arch/annotate-arm64.c
>> @@ -661,6 +661,20 @@ static void update_load_insn_state(struct type_state *state,
>>  	adjust_reg_index_state(state, dloc, dl, src);
>>  }
>>  
>> +/*
>> + * Match standard store variants (str, stur, stlr, stp) that follow
>> + * straightforward store semantics: source registers on the left (read-only)
>> + * and memory target on the right. Excludes exclusive stores (stxr, stxp, etc.)
>> + * which have status/result register side effects.
>> + */
>> +static bool is_standard_store_insn(const char *name)
>> +{
>> +	return !strncmp(name, "str", 3)  ||  /* str, strb, strh */
>> +	       !strncmp(name, "stur", 4) ||  /* stur, sturb, sturh */
>> +	       !strncmp(name, "stlr", 4) ||  /* stlr, stlrb, stlrh */
>> +	       !strncmp(name, "stp", 3);     /* stp */
>> +}
>> +
>>  static void update_insn_state_arm64(struct type_state *state,
>>  				    struct data_loc_info *dloc, Dwarf_Die *cu_die,
>>  				    struct disasm_line *dl)
>> @@ -742,6 +756,17 @@ static void update_insn_state_arm64(struct type_state *state,
>>  	/* Memory to register transfers */
>>  	if (is_standard_load_insn(dl->ins.name))
>>  		update_load_insn_state(state, dloc, dl, src, dst);
>> +	/* Register to memory transfers */
>> +	else if (is_standard_store_insn(dl->ins.name)) {
>> +		/*
>> +		 * Ignore transfers since it'd set a value in a struct
>> +		 * and won't change the type.
>> +		 *
>> +		 * Needs to update the pre-index and post-index addressing
>> +		 * modes for the destination register.
>> +		 */
>> +		adjust_reg_index_state(state, dloc, dl, dst);
>> +	}
>>  }
>>  #endif
>>  
>> -- 
>> 2.34.1
>>