Re: [PATCH 06/10] iio: frequency: ad9910: add axi backend driver

[Nuno Sá]

On Thu, 15 Oct 2026 13:49:46 -0300, Rodrigo Alencar <rodrigo.alencar@xxxxxxxxxx> wrote:
> Add the driver for the AD9910 AXI backend IP core, which interfaces with
> the data and control pins of the AD9910 DDS. It registers as an IIO
> backend that provides:
> 
> - a DMA output buffer that streams data into the parallel data port;
> - the parallel data destination (F[1:0] pins) and data rate, derived
>   from the PDCLK frequency;
> - the PROFILE[2:0] pins control, through profile channel enables.
> 
> It also registers a PWM chip with a single output driving the DRCTL
> pin, which the AD9910 driver uses to control the digital ramp generator
> direction. PWM period and duty cycle are programmed in PDCLK cycles.
> 
> Signed-off-by: Rodrigo Alencar <rodrigo.alencar@xxxxxxxxxx>

I think all sashiko findings are sensible! For the division by 0 does it
make sense to start with some default rate (so we do not have to care on
the read side)? Or maybe we're already guaranteed the core has some non
zero default value (but in that case not sure if we should trust the HW
- at least a comment would be useful).

-- 
Nuno Sá <nuno.sa@xxxxxxxxxx>