Re: [PATCH v3 6/6] hwmon: (peci/dimmtemp) Add support for Granite Rapids (GNR)

[Winiarska, Iwona]

On Thu, 2026-10-08 at 03:06 -0700, Changhuang Liang wrote:
> Add support for Granite Rapids (GNR) platform in PECI DIMM temperature
> monitoring driver.
> 
> The GNR platform has different DIMM topology from previous generations,
> with 12 channel ranks (CHAN_RANK_MAX_ON_GNR) and 2 DIMM indexes per
> channel. Define these new constants and update CHAN_RANK_MAX to use
> the GNR value since it represents the maximum across all supported
> platforms.
> 
> Since the current peci core does not support domains, accessing GNR's
> DIMM_TEMP_MAX and DIMM_TEMP_CRIT via PECI commands will be rejected
> and return completion code 0x90 (invalid request). To handle this, the
> read_thresholds callback is not defined for GNR, and the visibility
> logic is updated to skip exposing the max and crit temperature
> attributes.
> 
> The minimum PECI revision required for GNR is 0x42.
> 
> Signed-off-by: Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>

Reviewed-by: Iwona Winiarska <iwona.winiarska@xxxxxxxxx>

Thanks
-Iwona

> ---
>  drivers/hwmon/peci/dimmtemp.c | 33 +++++++++++++++++++++++++++++----
>  1 file changed, 29 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c
> index bd3e8715dfec..791a8e866081 100644
> --- a/drivers/hwmon/peci/dimmtemp.c
> +++ b/drivers/hwmon/peci/dimmtemp.c
> @@ -34,8 +34,10 @@
>  #define DIMM_IDX_MAX_ON_SPR	2
>  #define CHAN_RANK_MAX_ON_EMR	8
>  #define DIMM_IDX_MAX_ON_EMR	2
> +#define CHAN_RANK_MAX_ON_GNR	12
> +#define DIMM_IDX_MAX_ON_GNR	2
>  
> -#define CHAN_RANK_MAX		CHAN_RANK_MAX_ON_HSX
> +#define CHAN_RANK_MAX		CHAN_RANK_MAX_ON_GNR
>  #define DIMM_IDX_MAX		DIMM_IDX_MAX_ON_HSX
>  #define DIMM_NUMS_MAX		(CHAN_RANK_MAX * DIMM_IDX_MAX)
>  
> @@ -198,10 +200,18 @@ static umode_t dimmtemp_is_visible(const void *data,
> enum hwmon_sensor_types typ
>  {
>  	const struct peci_dimmtemp *priv = data;
>  
> -	if (test_bit(channel, priv->dimm_mask))
> -		return 0444;
> +	if (!test_bit(channel, priv->dimm_mask))
> +		return 0;
>  
> -	return 0;
> +	/*
> +	 * Some platforms do not provide the DIMM temperature thresholds over
> +	 * PECI - do not expose the corresponding attributes there.
> +	 */
> +	if ((attr == hwmon_temp_max || attr == hwmon_temp_crit) &&
> +	    !priv->gen_info->read_thresholds)
> +		return 0;
> +
> +	return 0444;
>  }
>  
>  static const struct hwmon_ops peci_dimmtemp_ops = {
> @@ -626,6 +636,17 @@ static const struct dimm_info dimm_emr = {
>  	.read_thresholds = &read_thresholds_emr,
>  };
>  
> +static const struct dimm_info dimm_gnr = {
> +	.chan_rank_max	= CHAN_RANK_MAX_ON_GNR,
> +	.dimm_idx_max	= DIMM_IDX_MAX_ON_GNR,
> +	.min_peci_revision = 0x42,
> +	/*
> +	 * Reading DIMM_TEMP_MAX/DIMM_TEMP_CRIT over PECI is answered with
> +	 * completion code 0x90 (invalid request) on Granite Rapids, so the
> +	 * threshold attributes are not exposed on this platform.
> +	 */
> +};
> +
>  static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
>  	{
>  		.name = "peci_cpu.dimmtemp.hsx",
> @@ -659,6 +680,10 @@ static const struct auxiliary_device_id
> peci_dimmtemp_ids[] = {
>  		.name = "peci_cpu.dimmtemp.emr",
>  		.driver_data = (kernel_ulong_t)&dimm_emr,
>  	},
> +	{
> +		.name = "peci_cpu.dimmtemp.gnr",
> +		.driver_data = (kernel_ulong_t)&dimm_gnr,
> +	},
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids);