Re: [PATCH v8 4/6] alpha: decode and acknowledge Tsunami system machine checks

[Matt Turner]

On Thu, Oct 15, 2026 at 6:24 AM Magnus Lindholm <linmag7@xxxxxxxxx> wrote:
> On system vectors 660/620, capture live PERROR and MISC before acknowledging

A few lines in the commit message are over 75 columns (this one, and
the ones starting "previously latched" and "by HRM 8.8.2.6"). checkpatch
complains about them.

[...]

> +     tsunami_ack_pchip(TSUNAMI_pchip0, state->perror[0]);
> +     /* Do not access the second Pchip on single-Pchip systems. */
> +     if (pchip1)
> +             tsunami_ack_pchip(TSUNAMI_pchip1, state->perror[1]);

Not something I'd hold the patch for, but the same 10.2.5.6 paragraph
you now cite for CPU vectors applies here to the Pchip that didn't
raise this machine check. If it latched an error that hasn't reached
DRIR yet, we can read it with INV set, print "Transaction information
unavailable", and then clear it, so its own interrupt with valid
SYN/CMD/ADDR never comes.

Acking only the Pchip(s) that SESF names would avoid that, at the cost
of the case where the frame is older than the live state. I'm fine
with either; I just want to know it was a deliberate choice. If it was,
maybe a sentence in the comment.

[...]

> +     struct tsunami_error_state live;

live is now only filled in on 660/620 and only read under the same
condition, so this is correct. Initializing it with = {} would keep it
that way if someone later moves the tsunami_report_live_errors() call
out of that branch.

With or without those changes:

Reviewed-by: Matt Turner <mattst88@xxxxxxxxx>

(no need to send a v9)