Re: [PATCH v3 0/4] qcom: videocc: Fix sleep clock on Glymur/SM8750/Nord

[Bartosz Golaszewski]

On Sat, 17 Oct 2026 06:58:13 +0200, Shawn Guo
<shengchao.guo@xxxxxxxxxxxxxxxx> said:
> The video clock controller on Glymur, SM8750 and Nord has three clock
> inputs: the board XO, the active-only board XO that feeds its PLL
> reference, and the 32 kHz chip sleep clock that sources its sleep clock
> generator. It has no AHB clock input; the AHB clock the controller uses
> for itself is generated inside the block from the XO input.
>
> qcom,sm8450-videocc.yaml describes two inputs for every compatible it
> covers, a board XO and a video AHB clock from GCC. For these three SoCs
> that leaves the sleep clock input undescribable, and describes as the
> second input a clock that is not routed into the controller.
>
> Patch 1 describes the three inputs for the Glymur, Nord and SM8750
> compatibles and keeps the two-input description for the rest. Patches
> 2-4 bring the Glymur, SM8750 and Nord videocc nodes in line with it.
> None of the DTS changes is a functional change.
>

Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxxxxxxxx>