Re: [PATCH net-next] net: phy: Add JLSemi JL21xx Gigabit Ethernet PHY driver

[Andrew Lunn]

On Tue, Oct 20, 2026 at 05:15:23PM +0000, netdev-bot+sashiko@xxxxxxxxxx wrote:
> Thank you for your contribution! Sashiko AI review found 10 potential
> issue(s) to consider.
> 
> Critical: 0 · High: 1 · Medium: 6 · Low: 3
> 
> If you believe none of the issues are legitimate, please reply to each
> issue of Medium severity or higher and explain why the AI is wrong.
> If any of them are legitimate and you plan to respin, please let patchwork
> know by including "pw-bot: cr" as a separate line at the end of your reply
> (one such reply per series is enough).
> 
> - [High] jlsemi_set_wol() can leave the MDIO bus mutex held permanently.
> - [Medium] Wake-on-LAN cannot work, yet the driver tells userspace it is
>   enabled.
> - [Medium] When WoL is enabled, jlsemi_set_wol() writes JLSEMI_WOL_RMSQ
>   (0x1fff) to page 0xd8a reg 17.
> - [Medium] jlsemi_config_init() always calls
>   jlsemi_disable_autonomous_eee() (clears PHYCR2 bit 5) on every…
> - [Medium] When the LED's three link-speed bits are all set,
>   jlsemi_led_hw_control_get() returns TRIGGER_NETDEV_LINK_10, LINK_100…
> - [Medium] jlsemi_set_wol() ignores every hardware-programming error and
>   always returns 0.
> - [Medium] In the interrupt-disable branch of jlsemi_config_intr(), `err
>   = phy_write_paged(phydev, JLSEMI_INER_PAGE, JLSEMI_INER, 0)` is never…
> - [Low] The register map and most of the logic in
>   drivers/net/phy/jlsemi.c are a near-verbatim copy of the RTL8211F…
> - [Low] jlsemi_config_rgmii_delay() handles rx-/tx-internal-delay-ps
>   inconsistently.
> - [Low] jlsemi_handle_interrupt() reads INSR (0x1d) once.
> 
> --
> 
> net: phy: Add JLSemi JL21xx Gigabit Ethernet PHY driver
> 
> This commit adds a new phylib driver for the JLSemi JL2101, JL2121 and
> generic JL21xx Gigabit PHYs. It covers paged register access, RGMII delay
> configuration, vendor status register parsing, interrupts, hardware LED
> control, magic packet Wake-on-LAN, autonomous EEE disable and
> suspend/resume.
> 
> Link: https://www.jlsemi.com/
> 
> > diff --git a/drivers/net/phy/jlsemi.c b/drivers/net/phy/jlsemi.c
> > new file mode 100644
> > index 0000000000000..c3acff48d4618
> > --- /dev/null
> > +++ b/drivers/net/phy/jlsemi.c
> > @@ -0,0 +1,551 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Driver for JLSemi Gigabit Ethernet PHYs (JL2121 / JL2101)
> > + *
> > + * Copyright (C) 2026 Pufan Jin <cyan2254650260@xxxxxxxxx>
> > + */
> 
> [ ... ]
> 
> > +/* Wake-on-LAN settings */
> > +#define JLSEMI_WOL_PAGE			0xd8a
> > +#define JLSEMI_WOL_SETTINGS_EVENTS	16
> > +#define JLSEMI_WOL_EVENT_MAGIC		BIT(12)
> > +#define JLSEMI_WOL_RST_RMSQ		17
> > +#define JLSEMI_WOL_RG_RSTB		BIT(15)
> > +#define JLSEMI_WOL_RMSQ			0x1fff
> 
> [Severity: Low]
> This isn't a bug, but the register map looks identical to the RTL8211F
> support in drivers/net/phy/realtek/realtek_main.c. That covers PHYCR2 0x19
> bit 5, INSR 0x1d, INER page 0xa42 reg 0x12, RGMII page 0xd08 regs
> 0x11/0x15, WoL page 0xd8a regs 16/17 with RG_RSTB BIT(15) and RMSQ 0x1fff,
> MAC page 0xd8c, and LEDCR page 0xd04 reg 0x10 with 5-bit per-LED fields.
> 
> jlsemi_led_hw_is_supported() and jlsemi_led_hw_control_get() also follow
> rtl8211x_led_hw_is_supported() and rtl8211f_led_hw_control_get() closely.
> The same goes for the set_wol, suspend and resume flows.

Interesting. Please see if this really is register compatible. If it
is, please extend the RTL8211F to cover this device.

    Andrew