[PATCH 11/12] drm/msm/a8xx: Switch to generated protect regs
From: Rob Clark
Date: Tue Oct 20 2026 - 16:51:07 EST
These also fix some perfcntr SEL regs which were mistakenly blocked
since we previously just copied the protect tables from downstream kgsl
(and only sometimes remembered to fix these).
Signed-off-by: Rob Clark <robin.clark@xxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/msm/adreno/a8xx_catalog.c | 301 +---------------------
1 file changed, 13 insertions(+), 288 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a8xx_catalog.c b/drivers/gpu/drm/msm/adreno/a8xx_catalog.c
index bc79013165c1..5f5f71d86df9 100644
--- a/drivers/gpu/drm/msm/adreno/a8xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a8xx_catalog.c
@@ -18,58 +18,6 @@
#include "catalog/adreno_milos.h"
#include "catalog/adreno_pakala.h"
-static const u32 a830_protect_regs[] = {
- A6XX_PROTECT_RDONLY(0x00000, 0x03a3),
- A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
- A6XX_PROTECT_NORDWR(0x00440, 0x001f),
- A6XX_PROTECT_RDONLY(0x00580, 0x005f),
- A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
- A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
- A6XX_PROTECT_RDONLY(0x00759, 0x0026),
- A6XX_PROTECT_RDONLY(0x00789, 0x0000),
- A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
- A6XX_PROTECT_NORDWR(0x00800, 0x0029),
- A6XX_PROTECT_NORDWR(0x00837, 0x00af),
- A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
- A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
- A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
- A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
- A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
- A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
- A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
- A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
- A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
- A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff),
- A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
- A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
- A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
- A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
- A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
- A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
- A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
- A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
- A6XX_PROTECT_NORDWR(0x0ae00, 0x0000),
- A6XX_PROTECT_NORDWR(0x0ae02, 0x0004),
- A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
- A6XX_PROTECT_NORDWR(0x0ae10, 0x036f),
- A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
- A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
- A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
- A6XX_PROTECT_NORDWR(0x18400, 0x003f),
- A6XX_PROTECT_RDONLY(0x18440, 0x013f),
- A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
- A6XX_PROTECT_RDONLY(0x1f878, 0x0787),
- A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
- A6XX_PROTECT_NORDWR(0x20000, 0x1fff),
- A6XX_PROTECT_NORDWR(0x27800, 0x007f),
- A6XX_PROTECT_RDONLY(0x27880, 0x0381),
- A6XX_PROTECT_NORDWR(0x27882, 0x0001),
- A6XX_PROTECT_NORDWR(0x27c02, 0x0000),
-};
-DECLARE_ADRENO_PROTECT(a830_protect, 64);
-
static const u32 a830_pwrup_reglist_regs[] = {
REG_A6XX_UCHE_MODE_CNTL,
REG_A8XX_UCHE_VARB_IDLE_TIMEOUT,
@@ -241,63 +189,6 @@ static const struct adreno_reglist_pipe a830_dyn_pwrup_reglist_regs[] = {
};
DECLARE_ADRENO_REGLIST_PIPE_LIST(a830_dyn_pwrup_reglist);
-static const u32 x285_protect_regs[] = {
- A6XX_PROTECT_RDONLY(0x00008, 0x039b),
- A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
- A6XX_PROTECT_NORDWR(0x00440, 0x001f),
- A6XX_PROTECT_RDONLY(0x00580, 0x005f),
- A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
- A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
- A6XX_PROTECT_RDONLY(0x00759, 0x0026),
- A6XX_PROTECT_RDONLY(0x00789, 0x0000),
- A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
- A6XX_PROTECT_NORDWR(0x00800, 0x0029),
- A6XX_PROTECT_NORDWR(0x0082c, 0x0000),
- A6XX_PROTECT_NORDWR(0x00837, 0x00af),
- A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
- A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
- A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
- A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
- A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
- A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
- A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
- A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
- A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
- A6XX_PROTECT_RDONLY(0x03cc6, 0x0039),
- A6XX_PROTECT_NORDWR(0x03d00, 0x1fff),
- A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
- A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
- A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
- A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
- A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
- A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
- A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
- A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
- A6XX_PROTECT_NORDWR(0x0a82e, 0x0000),
- A6XX_PROTECT_NORDWR(0x0ae00, 0x0006),
- A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
- A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf),
- A6XX_PROTECT_RDONLY(0x0aed0, 0x002f),
- A6XX_PROTECT_NORDWR(0x0af00, 0x027f),
- A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
- A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
- A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
- A6XX_PROTECT_NORDWR(0x18400, 0x003f),
- A6XX_PROTECT_RDONLY(0x18440, 0x013f),
- A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
- A6XX_PROTECT_RDONLY(0x1f878, 0x0507),
- A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
- A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff),
- A6XX_PROTECT_NORDWR(0x27800, 0x007f),
- A6XX_PROTECT_RDONLY(0x27880, 0x0385),
- A6XX_PROTECT_NORDWR(0x27882, 0x000a),
- A6XX_PROTECT_NORDWR(0x27c06, 0x0000),
-};
-
-DECLARE_ADRENO_PROTECT(x285_protect, 15);
-
static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = {
{ REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
@@ -336,57 +227,6 @@ static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = {
};
DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist);
-static const u32 a810_protect_regs[] = {
- A6XX_PROTECT_RDONLY(0x00000, 0x03a3),
- A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
- A6XX_PROTECT_NORDWR(0x00440, 0x001f),
- A6XX_PROTECT_RDONLY(0x00580, 0x005f),
- A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
- A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
- A6XX_PROTECT_RDONLY(0x00759, 0x0026),
- A6XX_PROTECT_RDONLY(0x00789, 0x0000),
- A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
- A6XX_PROTECT_NORDWR(0x00800, 0x0029),
- A6XX_PROTECT_NORDWR(0x00837, 0x00af),
- A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
- A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
- A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
- A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
- A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
- A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
- A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
- A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
- A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
- A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff),
- A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
- A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
- A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
- A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
- A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
- A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
- A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
- A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
- A6XX_PROTECT_NORDWR(0x0ae00, 0x0006),
- A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
- A6XX_PROTECT_NORDWR(0x0ae10, 0x036f),
- A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
- A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
- A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
- A6XX_PROTECT_NORDWR(0x18400, 0x003f),
- A6XX_PROTECT_RDONLY(0x18440, 0x013f),
- A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
- A6XX_PROTECT_RDONLY(0x1f878, 0x0787),
- A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
- A6XX_PROTECT_NORDWR(0x20000, 0x1fff),
- A6XX_PROTECT_NORDWR(0x27800, 0x007f),
- A6XX_PROTECT_RDONLY(0x27880, 0x0381),
- A6XX_PROTECT_NORDWR(0x27882, 0x0001),
- A6XX_PROTECT_NORDWR(0x27c02, 0x0000),
-};
-DECLARE_ADRENO_PROTECT(a810_protect, 64);
-
static const uint32_t a810_pwrup_reglist_regs[] = {
REG_A6XX_UCHE_MODE_CNTL,
REG_A8XX_UCHE_VARB_IDLE_TIMEOUT,
@@ -626,64 +466,6 @@ struct a6xx_hfi_limits_tbl x285_limits_tbl[] = {
};
DECLARE_ADRENO_LIMITS_TABLE(x285_limits);
-static const u32 a840_protect_regs[] = {
- A6XX_PROTECT_RDONLY(0x00008, 0x039b),
- A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
- A6XX_PROTECT_NORDWR(0x00440, 0x001f),
- A6XX_PROTECT_RDONLY(0x00580, 0x005f),
- A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
- A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
- A6XX_PROTECT_RDONLY(0x00759, 0x001b),
- A6XX_PROTECT_NORDWR(0x00775, 0x000a),
- A6XX_PROTECT_RDONLY(0x00789, 0x0000),
- A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
- A6XX_PROTECT_NORDWR(0x00800, 0x0029),
- A6XX_PROTECT_NORDWR(0x00837, 0x00af),
- A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
- A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
- A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
- A6XX_PROTECT_NORDWR(0x00c07, 0x0008),
- A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
- A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
- A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
- A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
- A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
- A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
- A6XX_PROTECT_RDONLY(0x03cc6, 0x0039),
- A6XX_PROTECT_NORDWR(0x03d00, 0x1fff),
- A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
- A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
- A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
- A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
- A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
- A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
- A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
- A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
- A6XX_PROTECT_NORDWR(0x0a82e, 0x0000),
- A6XX_PROTECT_NORDWR(0x0ae00, 0x0000),
- A6XX_PROTECT_NORDWR(0x0ae02, 0x0004),
- A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
- A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf),
- A6XX_PROTECT_RDONLY(0x0aed0, 0x002f),
- A6XX_PROTECT_NORDWR(0x0af00, 0x027f),
- A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
- A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
- A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
- A6XX_PROTECT_NORDWR(0x18400, 0x003f),
- A6XX_PROTECT_RDONLY(0x18440, 0x013f),
- A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
- A6XX_PROTECT_RDONLY(0x1f878, 0x0507),
- A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
- A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff),
- A6XX_PROTECT_NORDWR(0x27800, 0x007f),
- A6XX_PROTECT_RDONLY(0x27880, 0x0385),
- A6XX_PROTECT_NORDWR(0x27882, 0x0009),
- A6XX_PROTECT_NORDWR(0x27c06, 0x0000),
-};
-DECLARE_ADRENO_PROTECT(a840_protect, 15);
-
static const struct adreno_reglist a840_gbif[] = {
{ REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 },
{ REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 },
@@ -956,67 +738,6 @@ struct a6xx_hfi_limits_tbl a840_limits_tbl[] = {
};
DECLARE_ADRENO_LIMITS_TABLE(a840_limits);
-static const u32 a850_protect_regs[] = {
- A6XX_PROTECT_RDONLY(0x00008, 0x039b),
- A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
- A6XX_PROTECT_NORDWR(0x00440, 0x001f),
- A6XX_PROTECT_RDONLY(0x00580, 0x005f),
- A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
- A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
- A6XX_PROTECT_RDONLY(0x00759, 0x001b),
- A6XX_PROTECT_NORDWR(0x00775, 0x000a),
- A6XX_PROTECT_RDONLY(0x00789, 0x0000),
- A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
- A6XX_PROTECT_NORDWR(0x00800, 0x0029),
- A6XX_PROTECT_NORDWR(0x00837, 0x00af),
- A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
- A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
- A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
- A6XX_PROTECT_NORDWR(0x00c07, 0x0008),
- A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
- A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
- A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
- A6XX_PROTECT_NORDWR(0x00df5, 0x0003),
- A6XX_PROTECT_RDONLY(0x00df9, 0x0007),
- A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
- A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
- A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
- A6XX_PROTECT_RDONLY(0x03cc6, 0x0039),
- A6XX_PROTECT_NORDWR(0x03d00, 0x1fff),
- A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
- A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
- A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
- A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
- A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
- A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
- A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
- A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
- A6XX_PROTECT_NORDWR(0x0a82e, 0x0000),
- A6XX_PROTECT_NORDWR(0x0ae00, 0x0000),
- A6XX_PROTECT_NORDWR(0x0ae02, 0x0004),
- A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
- A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf),
- A6XX_PROTECT_RDONLY(0x0aed0, 0x002f),
- A6XX_PROTECT_NORDWR(0x0af00, 0x027f),
- A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
- A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
- A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
- A6XX_PROTECT_NORDWR(0x18400, 0x003f),
- A6XX_PROTECT_RDONLY(0x18440, 0x013f),
- A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1ac00, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1cc00, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
- A6XX_PROTECT_RDONLY(0x1f878, 0x0507),
- A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
- A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff),
- A6XX_PROTECT_NORDWR(0x27800, 0x007f),
- A6XX_PROTECT_RDONLY(0x27880, 0x0385),
- A6XX_PROTECT_NORDWR(0x27882, 0x0035),
- A6XX_PROTECT_NORDWR(0x27c06, 0x0000),
-};
-DECLARE_ADRENO_PROTECT(a850_protect, 15);
-
static const u32 a850_pwrup_reglist_regs[] = {
REG_A8XX_RB_CMP_NC_MODE_CNTL,
REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN,
@@ -1215,7 +936,7 @@ static const struct adreno_info a8xx_gpus[] = {
ADRENO_QUIRK_IFPC,
.funcs = &a8xx_gpu_funcs,
.a6xx = &(const struct a6xx_info) {
- .protect = &a830_protect,
+ .protect = &pakala_protect,
.nonctxt_reglist = pakala_nonctxt_regs,
.pwrup_reglist = &a830_pwrup_reglist,
.dyn_pwrup_reglist = &a830_dyn_pwrup_reglist,
@@ -1260,7 +981,7 @@ static const struct adreno_info a8xx_gpus[] = {
ADRENO_QUIRK_SOFTFUSE,
.funcs = &a8xx_gpu_funcs,
.a6xx = &(const struct a6xx_info) {
- .protect = &x285_protect,
+ .protect = &glymur_protect,
.nonctxt_reglist = glymur_nonctxt_regs,
.pwrup_reglist = &a840_pwrup_reglist,
.dyn_pwrup_reglist = &x285_dyn_pwrup_reglist,
@@ -1305,7 +1026,7 @@ static const struct adreno_info a8xx_gpus[] = {
ADRENO_QUIRK_IFPC,
.funcs = &a8xx_gpu_funcs,
.a6xx = &(const struct a6xx_info) {
- .protect = &a840_protect,
+ .protect = &pakala_protect,
.nonctxt_reglist = kaanapali_nonctxt_regs,
.pwrup_reglist = &a840_pwrup_reglist,
.dyn_pwrup_reglist = &a840_dyn_pwrup_reglist,
@@ -1351,7 +1072,7 @@ static const struct adreno_info a8xx_gpus[] = {
.funcs = &a8xx_gpu_funcs,
.zapfw = "gen80300_zap.mbn",
.a6xx = &(const struct a6xx_info) {
- .protect = &a810_protect,
+ .protect = &milos_protect,
.nonctxt_reglist = milos_nonctxt_regs,
.pwrup_reglist = &a810_pwrup_reglist,
.dyn_pwrup_reglist = &a810_dyn_pwrup_reglist,
@@ -1394,7 +1115,7 @@ static const struct adreno_info a8xx_gpus[] = {
ADRENO_QUIRK_SOFTFUSE,
.funcs = &a8xx_gpu_funcs,
.a6xx = &(const struct a6xx_info) {
- .protect = &x285_protect,
+ .protect = &glymur_protect,
.nonctxt_reglist = glymur_nonctxt_regs,
.pwrup_reglist = &a840_pwrup_reglist,
.dyn_pwrup_reglist = &x285_dyn_pwrup_reglist,
@@ -1437,7 +1158,7 @@ static const struct adreno_info a8xx_gpus[] = {
ADRENO_QUIRK_IFPC,
.funcs = &a8xx_gpu_funcs,
.a6xx = &(const struct a6xx_info) {
- .protect = &a850_protect,
+ .protect = &maili_protect,
.nonctxt_reglist = maili_nonctxt_regs,
.pwrup_reglist = &a850_pwrup_reglist,
.dyn_pwrup_reglist = &a850_dyn_pwrup_reglist,
@@ -1481,7 +1202,7 @@ static const struct adreno_info a8xx_gpus[] = {
ADRENO_QUIRK_IFPC,
.funcs = &a8xx_gpu_funcs,
.a6xx = &(const struct a6xx_info) {
- .protect = &a850_protect,
+ .protect = &hawi_protect,
.nonctxt_reglist = hawi_nonctxt_regs,
.pwrup_reglist = &a850_pwrup_reglist,
.dyn_pwrup_reglist = &a850_dyn_pwrup_reglist,
@@ -1516,6 +1237,10 @@ DECLARE_ADRENO_GPULIST(a8xx);
static inline __always_unused void __build_asserts(void)
{
- BUILD_BUG_ON(a810_protect.count > a810_protect.count_max);
- BUILD_BUG_ON(a830_protect.count > a830_protect.count_max);
+ BUILD_BUG_ON(glymur_protect.count > glymur_protect.count_max);
+ BUILD_BUG_ON(hawi_protect.count > hawi_protect.count_max);
+ BUILD_BUG_ON(kaanapali_protect.count > kaanapali_protect.count_max);
+ BUILD_BUG_ON(maili_protect.count > maili_protect.count_max);
+ BUILD_BUG_ON(milos_protect.count > milos_protect.count_max);
+ BUILD_BUG_ON(pakala_protect.count > pakala_protect.count_max);
}
--
2.56.0