Re: [PATCH v3 2/4] clk: amlogic: Improve the issue of PLL lock failures

[John O'Callaghan]

Hi Chuan,

Jerome asked what was tested; here is a G12A data point.

On a Radxa Zero (S905Y2, G12A) running v7.3, sys_pll_dco occasionally
fails to lock on cpufreq transitions, at room temperature:

  meson_clk_pll_set_rate: pll sys_pll_dco didn't lock, trying to set old rate 6000000000

It happens with all the sys_pll OPPs (old DCO rates 3216, 3408, 3600,
4800, 5592 and 6000 MHz) but, here, only while the video decoder is
busy. Reproducer: the userspace governor, random writes of the
1200-1800 MHz OPPs to scaling_setspeed (~700 transitions/s), with a
GStreamer v4l2 decode loop (meson vdec, H.264 + VP9 1080p) running
alongside. 46 C SoC temperature.

                                       transitions   lock failures
  v7.3                                     500290        33
  v7.3, no decoder running                 250056         0
  v7.3 + this series (1-4)                 500089         0
  v7.3 + patch 2/4 only                    500066         0

So on G12A it is the 20 us delays of this patch that make the
difference.

Tested-by: John O'Callaghan <johnocallaghan@xxxxxxxxx> # Radxa Zero (G12A)

The testing was scripted with the help of an LLM coding assistant; I
ran it on my board and checked the results.

Thanks,
John