Re: [PATCH] clk: qcom: gcc-ipq6018: add fallback names for the bias PLL parents

[Konrad Dybcio]

On 10/20/26 8:54 AM, Julius Bairaktaris wrote:
> From: Vladyslav Andreichykov <vladdrako007@xxxxxxxxx>
> 
> bias_pll_cc_clk and bias_pll_nss_noc_clk are outputs of the CMN PLL,
> which takes its AHB and SYS clocks from GCC, so the device tree does not
> pass them back to GCC. With only .fw_name these parents never resolve,
> nss_ppe_clk_src stays an orphan, and setting it to 300 MHz fails with
> -EINVAL. The NSS clocks below it, such as gcc_nss_edma_clk, read 0 Hz.

Because this is a "never could have worked" situation, we should
properly fix it by adding the DT references to those clocks. This
way we also get fw_devlink which will ensure the probe ordering
is right.

Konrad