[PATCH 3/3] arm64: dts: imx8mp: Move board Root Port children under &pcie0_port0
From: Sherry Sun (OSS)
Date: Wed Oct 21 2026 - 05:03:38 EST
From: Sherry Sun <sherry.sun@xxxxxxx>
Commit 396fbe9a028d ("arm64: dts: imx8mp: Add Root Port node and PERST
property") added a Root Port node pcie@0 to the SoC level host bridge.
However, some boards already described the Root Port with a different
node name:
imx8mp-venice-gw72xx/gw73xx/gw82xx.dtsi: pcie@0,0
imx8mp-hummingboard-pulse.dts: root@0,0
Both nodes now share devfn 0 under the same host bridge.
of_pci_find_child_device() returns the first match, which is the SoC
pcie@0 node, so the board level Root Port node and all of its children
become stale. Also, for the Gateworks boards, since both nodes have
device_type = "pci", pci_host_common_parse_ports() registers two Root
Ports for the same port.
Fix this by moving the children of the board level Root Port nodes
under &pcie0_port0 and dropping the duplicated board level Root Port
nodes.
The moved nodes are now located on the secondary bus of the Root Port
(bus 1), so update their reg bus number and unit addresses accordingly
to keep dtc pci_device_reg/pci_device_bus_num checks happy. Only the
devfn is used to match the PCI device to its DT node, so this does not
change the matching.
Fixes: 396fbe9a028d ("arm64: dts: imx8mp: Add Root Port node and PERST property")
Reported-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
Closes: https://lore.kernel.org/all/171421fb-d0a6-4e3f-b2dc-226e9c548972@xxxxxxxxxxxxxx/
Signed-off-by: Sherry Sun <sherry.sun@xxxxxxx>
---
.../dts/freescale/imx8mp-hummingboard-pulse.dts | 17 ++++++-----------
.../boot/dts/freescale/imx8mp-venice-gw72xx.dtsi | 22 ++++++++--------------
.../boot/dts/freescale/imx8mp-venice-gw73xx.dtsi | 22 ++++++++--------------
.../boot/dts/freescale/imx8mp-venice-gw82xx.dtsi | 22 ++++++++--------------
4 files changed, 30 insertions(+), 53 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts
index d32844c3af05..911799db4b91 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts
@@ -59,18 +59,13 @@ &pcie {
pinctrl-names = "default";
reset-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
status = "okay";
+};
- root@0,0 {
- compatible = "pci16c3,abcd";
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
-
- /* Intel i210 */
- pcie_eth: ethernet@1,0 {
- compatible = "pci8086,157b";
- reg = <0x00010000 0 0 0 0>;
- };
+&pcie0_port0 {
+ /* Intel i210 */
+ pcie_eth: ethernet@0,0 {
+ compatible = "pci8086,157b";
+ reg = <0x00010000 0 0 0 0>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
index 76020ef89bf3..224b494bc51d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
@@ -156,35 +156,29 @@ &pcie {
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
status = "okay";
+};
+&pcie0_port0 {
pcie@0,0 {
- reg = <0x0000 0 0 0 0>;
+ reg = <0x10000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
- pcie@0,0 {
- reg = <0x0000 0 0 0 0>;
+ pcie@3,0 {
+ reg = <0x1800 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
- pcie@3,0 {
- reg = <0x1800 0 0 0 0>;
- device_type = "pci";
+ eth1: ethernet@0,0 {
+ reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
-
- eth1: ethernet@0,0 {
- reg = <0x0000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
- local-mac-address = [00 00 00 00 00 00];
- };
+ local-mac-address = [00 00 00 00 00 00];
};
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
index 5eb114d2360a..c704a73cdb6e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
@@ -168,35 +168,29 @@ &pcie {
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
status = "okay";
+};
+&pcie0_port0 {
pcie@0,0 {
- reg = <0x0000 0 0 0 0>;
+ reg = <0x10000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
- pcie@0,0 {
- reg = <0x0000 0 0 0 0>;
+ pcie@4,0 {
+ reg = <0x2000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
- pcie@4,0 {
- reg = <0x2000 0 0 0 0>;
- device_type = "pci";
+ eth1: ethernet@0,0 {
+ reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
-
- eth1: ethernet@0,0 {
- reg = <0x0000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
- local-mac-address = [00 00 00 00 00 00];
- };
+ local-mac-address = [00 00 00 00 00 00];
};
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi
index 2b86cc62a41a..bb62a91b6029 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi
@@ -239,35 +239,29 @@ &pcie {
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
status = "okay";
+};
+&pcie0_port0 {
pcie@0,0 {
- reg = <0x0000 0 0 0 0>;
+ reg = <0x10000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
- pcie@0,0 {
- reg = <0x0000 0 0 0 0>;
+ pcie@7,0 {
+ reg = <0x3800 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
- pcie@7,0 {
- reg = <0x3800 0 0 0 0>;
- device_type = "pci";
+ eth1: ethernet@0,0 {
+ reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
-
- eth1: ethernet@0,0 {
- reg = <0x0000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
- local-mac-address = [00 00 00 00 00 00];
- };
+ local-mac-address = [00 00 00 00 00 00];
};
};
};
--
2.50.1