Re: [PATCH 4/4] clk: qcom: apss-ipq9650: Add IPQ9650 APSS clock controller driver

[Kathiravan Thirumoorthy]

On 10/16/2026 7:22 PM, Konrad Dybcio wrote:
> On 10/7/26 8:50 AM, Kathiravan Thirumoorthy wrote:
> > The APSS clock controller on IPQ9650 provides the CPU and L3 clocks.
> > The four Cortex-A55 cores (silver), the Cortex-A78 core (gold) and the
> > L3 are each clocked by their own Zonda PLL. Each clock is selected
> > through a glitch-free mux (GFM) whose parents are XO, GPLL0 and the
> > corresponding PLL. The gold mux can also select the PLL's post-divider
> [...]
>
> > +static struct clk_branch apss_silver_core_clk = {
> > +	.halt_reg = 0x8c,
> > +	.clkr = {
> > +		.enable_reg = 0x8c,
> > +		.enable_mask = BIT(0),
> > +		.hw.init = &(struct clk_init_data) {
> > +			.name = "apss_silver_clk",
> > +			.parent_hws = (const struct clk_hw*[]) {
> > +				&silver_apss_pll_gfmux.hw,
> > +			},
> > +			.num_parents = 1,
> > +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> Do the clocks have to be enabled even if the CPUs are offline?

Yes. The bootloader leaves these clocks enabled. Marking them with 
CLK_IS_CRITICAL prevents clk_disable_unused() from gating the CPU and L3 
clocks and hanging the system during boot.

> Konrad