[PATCH v4 6/7] dt-bindings: display: tegra: Document 8-bit CPU parallel interface

From: Svyatoslav Ryhel

Date: Thu Oct 22 2026 - 09:25:35 EST


Document 8-bit CPU parallel MIPI DBI Type B interface provided by
Tegra20/30 SoCs display controller.

Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
Signed-off-by: Svyatoslav Ryhel <clamor95@xxxxxxxxx>
---
.../display/tegra/nvidia,tegra20-dbi.yaml | 108 ++++++++++++++++++
.../display/tegra/nvidia,tegra20-dc.yaml | 15 +++
2 files changed, 123 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dbi.yaml

diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dbi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dbi.yaml
new file mode 100644
index 0000000000000..6b4fd20c5817c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dbi.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dbi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nvidia Tegra Display Controller based MIPI DBI Type B interface
+
+maintainers:
+ - Svyatoslav Ryhel <clamor95@xxxxxxxxx>
+
+description: The display controller in Tegra20/30 SoCs features an
+ 8-bit SPI interface that closely resembles the MIPI DBI Type B
+ protocol and is referred to as '8-bit CPU'. Each display controller
+ provides two such interfaces, which can be used to send MIPI DCS
+ commands to initialize and control the panel while image data is
+ transmitted via 16/18/24-line RGB.
+
+properties:
+ nvidia,index:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Number of DBI interface used 0 - primary, 1 - secondary. If
+ property is not set, primary will be used.
+ enum: [ 0, 1 ]
+
+ panel:
+ type: object
+ description: Node of supported panel driven by the bridge.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Video port for RGB input.
+
+ properties:
+ endpoint:
+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
+ unevaluatedProperties: false
+
+ properties:
+ bus-width:
+ enum: [ 16, 18, 24 ]
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Video port for DBI output (panel or connector).
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - panel
+ - ports
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dbi {
+ nvidia,index = <0>;
+
+ panel {
+ compatible = "hit,tx10d07vm0baa";
+
+ reset-gpios = <&gpio 175 GPIO_ACTIVE_LOW>;
+
+ avci-supply = <&vcc_2v8_lcd>;
+ iovcc-supply = <&iovcc_1v8_lcd>;
+
+ backlight = <&backlight>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&bridge_output>;
+ };
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ bridge_input: endpoint {
+ remote-endpoint = <&dpi_output>;
+ bus-width = <24>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ bridge_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
index 69be95afd5627..a014bf0dd508d 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
@@ -76,6 +76,9 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: A list of phandles of outputs that this display controller can drive.

+ dbi:
+ $ref: /schemas/display/tegra/nvidia,tegra20-dbi.yaml#
+
rgb:
type: object

@@ -155,6 +158,18 @@ allOf:
- const: wind
- const: wint

+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra114-dc
+ - nvidia,tegra124-dc
+ - nvidia,tegra210-dc
+ then:
+ properties:
+ dbi: false
+
additionalProperties: false

required:
--
2.53.0