Re: [PATCH] MIPS: SGI-IP27: Install the cache error vector on every CPU

[Maciej W. Rozycki]

On Wed, 21 Oct 2026, Imre Kaloz wrote:

> diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
> index 62733e049570..0fef66b86959 100644
> --- a/arch/mips/sgi-ip27/ip27-smp.c
> +++ b/arch/mips/sgi-ip27/ip27-smp.c
> @@ -133,6 +135,18 @@ static void ip27_init_cpu(void)
>  	per_cpu_init();
>  }
>  
> +static void ip27_init_secondary(void)
> +{
> +	/*
> +	 * The hub flips the low 128K of the attribute 0 uncached alias per
> +	 * CPU slice and the cache error vector is fetched through that alias,
> +	 * so the copy trap_init() made through TO_UNCAC() only serves slice 0.
> +	 */
> +	memcpy((void *)CKSEG1ADDR(0x100), (void *)TO_UNCAC(0x100), 0x80);

 This just copies instructions between the same physical memory locations, 
from an XKPHYS mapping to its corresponding KSEG1 mapping, i.e. the bus 
addresses are the same, so please give a more elaborate explanation how 
this is supposed to work.  I guess I'm just missing something, but that 
has to be obvious from the contribution itself, also for other people that 
may come across this change in the repo in the future.

 Also, please don't cc stable with submissions targeting mainline, fixes 
will be picked up for backporting based on the Cc: tag in the commit 
description.

  Maciej