Re: [PATCH v2 03/10] dt-bindings: iio: frequency: add adi,ad9910-axi-backend

[Conor Dooley]

On Fri, Oct 23, 2026 at 08:15:07AM -0300, Rodrigo Alencar wrote:
> On 22/10/26 19:38, Conor Dooley wrote:
> > On Thu, Oct 22, 2026 at 12:19:01PM -0300, Rodrigo Alencar via B4 Relay wrote:
> > > From: Rodrigo Alencar <rodrigo.alencar@xxxxxxxxxx>
> > > 
> > > Add bindings for the AD9910 AXI backend IP core. The FPGA IP core
> > > interfaces with the data and control pins of the AD9910 DDS, streaming
> > > data from memory via DMA into the 18-bit parallel data port (F[1:0] and
> > > D[15:0] pins), which is clocked by the PDCLK output of the device. It
> > > also drives the PROFILE[2:0] pins and the DRCTL pin, which controls the
> > > slope direction of the digital ramp generator (DRG). The DRCTL pin is
> > > driven by a PWM generator, so the IP core is described both as an IIO
> > > backend and as a PWM provider.
> 
> ...
> 
> > > +  '#io-backend-cells':
> > > +    const: 0
> > > +
> > > +  '#pwm-cells':
> > > +    const: 3
> > > +    description:
> > > +      The first cell must be 0, as only the DRCTL PWM output is available.
> > 
> > I was about to ack this, but the wording here caught my eye. Are there
> > other PWMs that are unavailable?
> 
> Not for this version of this core. Other signals to control the DDS could be
> modeled as PWM, e.g. DRHOLD, PROFILE0, OSK... but that is not being considered
> at this stage.

Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
pw-bot: not-applicable

(But maybe consider rewording so that it doesn't sound like there are
other PWMs that cannot be used)

> 
> > 
> > > +      The second cell is the PWM period in nanoseconds and the third cell
> > > +      holds the PWM flags.
> 
> -- 
> Kind regards,
> 
> Rodrigo Alencar

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