Re: [PATCH] MIPS: SGI-IP27: Install the cache error vector on every CPU

[Maciej W. Rozycki]

On Sat, 24 Oct 2026, Thomas Bogendoerfer wrote:

> > > diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
> > > index 62733e049570..0fef66b86959 100644
> > > --- a/arch/mips/sgi-ip27/ip27-smp.c
> > > +++ b/arch/mips/sgi-ip27/ip27-smp.c
> > > @@ -133,6 +135,18 @@ static void ip27_init_cpu(void)
> > >  	per_cpu_init();
> > >  }
> > >  
> > > +static void ip27_init_secondary(void)
> > > +{
> > > +	/*
> > > +	 * The hub flips the low 128K of the attribute 0 uncached alias per
> > > +	 * CPU slice and the cache error vector is fetched through that alias,
> > > +	 * so the copy trap_init() made through TO_UNCAC() only serves slice 0.
> > > +	 */
> > > +	memcpy((void *)CKSEG1ADDR(0x100), (void *)TO_UNCAC(0x100), 0x80);
> > 
> >  This just copies instructions between the same physical memory locations, 
> > from an XKPHYS mapping to its corresponding KSEG1 mapping, i.e. the bus 
> 
> IP27 is special here:
> 
> /*
>  * IP27 uses the R10000's uncached attribute feature.  Attribute 3 selects
>  * uncached memory addressing. Hide the definitions on 32-bit compilation
>  * of the compat-vdso code.
>  */
> #ifdef CONFIG_64BIT
> #define HSPEC_BASE              _AC(0x9000000000000000, UL)
> #define IO_BASE                 _AC(0x9200000000000000, UL)
> #define MSPEC_BASE              _AC(0x9400000000000000, UL)
> #define UNCAC_BASE              _AC(0x9600000000000000, UL)
> #define CAC_BASE                _AC(0xa800000000000000, UL)
> #endif
> 
> Hub ASIC uses the extra address bits, so the physiacl address is not the same.

 Fair enough, though I think that the use of the R10k's uncached attribute 
driven on the bus for what I gather is each CPU's local memory (?) will 
best be documented more clearly through the change (i.e. in the commit 
description and with ip27_init_secondary()).

  Maciej