[PATCH v2] MIPS: cpu-probe: Recognise the XBurst core of the Ingenic X1600

[Olivier Louvignes]

The X1600 reports PRId 0x00d00000: company Ingenic D0, implementation 0,
which cpu_probe_ingenic() rejects with "Unknown Ingenic Processor ID!"
before any console exists.

The value is in the X1600 programming manual, 2.2 "PRID of X1600-CPU":
"For X1600, its value is 0x00D0000", a digit short (the X1830 manual's
same sentence gives 0x00D00100); the chip reads 0x00d00000.

Add implementation 0 as PRID_IMP_XBURST and handle it as
PRID_IMP_XBURST_REV2, as for the X1830, which also reports company D0:
write-combine through the WA bit, and none of the REV1 workarounds.

Tested on a HiBy R1 (X1600) on v7.3: it reports "00d00000 (Ingenic
XBurst)", mips32r2 and 1099 BogoMIPS at 1104 MHz, and boots to userspace
straight from the boot ROM's USB loader after a reset, so without the
HPTLB_DIS write of the REV1 path.

Co-developed-by: H. Nikolaus Schaller <hns@xxxxxxxxxxxxx>
Signed-off-by: H. Nikolaus Schaller <hns@xxxxxxxxxxxxx>
Signed-off-by: Olivier Louvignes <olivier@xxxxxxxxx>
---

Notes:
    v2: the Letux kernel's handling (commits ee3e4e8baeb6 and b799b9a5e4d3,
    Nikolaus): no SoC in the macro name, and the REV2 path, as for the X1830.
    v1 put the X1600 on the REV1 path, which its commit message didn't say.
    Letux's PRID_IMP_XBURST2_R2 (X2600) is left out: I can't test it.
    Added the manual reference Maciej asked for.
    
    v1: https://lore.kernel.org/all/20261023204205.48222-1-olivier@xxxxxxxxx/

 arch/mips/include/asm/cpu.h  | 1 +
 arch/mips/kernel/cpu-probe.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 0fd9f9bbd21f..c43c9364ddd0 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -186,6 +186,7 @@
  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
  */
 
+#define PRID_IMP_XBURST		0x0000	/* XBurst®1 (X1600)			*/
 #define PRID_IMP_XBURST_REV1	0x0200	/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA	*/
 #define PRID_IMP_XBURST_REV2	0x0100	/* XBurst®1 with MXU2.0 SIMD ISA		*/
 #define PRID_IMP_XBURST2		0x2000	/* XBurst®2 with MXU2.1 SIMD ISA		*/
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 489612ed9d49..7da5591f6024 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1814,6 +1814,8 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 		}
 		fallthrough;
 
+	/* XBurst®1 (X1600) */
+	case PRID_IMP_XBURST:
 	/* XBurst®1 with MXU2.0 SIMD ISA */
 	case PRID_IMP_XBURST_REV2:
 		/* Ingenic uses the WA bit to achieve write-combine memory writes */

base-commit: bfe97f12a0a64c3682be21a02404238e3b91e945
-- 
2.39.5