[PATCH 0/2] clk: meson: s4: two peripheral clock fixes

[christian . koever-draxl]

From: Christian Stefan Kövér-Draxl <ckoever@xxxxxxxxxx>

Two fixes for the S4 peripheral clock controller found while bringing
up an S905W2 TV box:

 - the PWM muxes may pick vid_pll, which is reprogrammed on every HDMI
   mode set and so changes the period of any PWM that runs from it. On
   this board that corrupted the PWM CPU regulator (first cpufreq
   transition hung the SoC) and the 32.768 kHz clock of the SDIO wifi
   chip;
 - the CEC 32k selectors lack CLK_SET_RATE_PARENT, so AO-CEC cannot set
   its 32768 Hz rate and fails to probe.

Tool use (Documentation/process/generated-content.rst):
This work was done with the help of an AI coding assistant, Claude
(Anthropic), used through Claude Code over many sessions. It did a large
part of the hands-on work: it read the vendor kernel and the firmware
interfaces, probed registers on the board, drafted the code and the
changelogs, and ran the builds, checkpatch, dt_binding_check and the
tests on the hardware. I directed the work, reviewed every change and
the final patches, and take responsibility for them. There is no single
prompt to quote; the sessions were of the form "find out why X fails on
this board, fix it, test it on the box".

Tested on an Amediatech X98Q TV box (Amlogic S905W2, S4 family, 2 GiB),
vendor U-Boot and BL31/OP-TEE, Linux 7.3 plus this work.

Christian Stefan Kövér-Draxl (2):
  clk: meson: s4: keep the PWM clocks off vid_pll
  clk: meson: s4: propagate rate requests through the CEC 32k muxes

 drivers/clk/meson/s4-peripherals.c | 40 +++++++++++++++++++++---------
 1 file changed, 28 insertions(+), 12 deletions(-)


base-commit: 7be4bc52fd9e0e55dc9a2e0232b89427d2c4b614
-- 
2.56.0