[PATCH 0/2] serial: tegra: Fix 32-bit overflows in the clock rate adjustment
From: Patrick Fischer via B4 Relay
Date: Sun Oct 25 2026 - 18:50:47 EST
On 32-bit ARM, both the clock rate adjustment from
"nvidia,adjust-baud-rates" and the check of the resulting rate overflow
a 32-bit long at the high baud rates the adjustment is meant for. On
the Tegra Note 7 (Tegra114), Bluetooth at 3 Mbaud therefore ran with a
UART clock 5.6 % too low, and the check computed -0.18 % and let it
pass.
UART clock at 3 Mbaud with a tolerance of 136 for 1 to 4 Mbaud
(pll_p 408 MHz):
requested configured check
without patches 47.79 MHz 45.33 MHz -0.18 %
with patches 48.65 MHz 48.00 MHz 0.00 %
With both patches and the unchanged tolerance of 136, Bluetooth on the
Tegra Note 7 works at 3 Mbaud: the UART clock is 48.00 MHz, and the
WL1801 scans and connects to a paired device without HCI errors.
With a deliberately wrong tolerance of -500, which gives 45.33 MHz at
3 Mbaud, the check now reports the deviation (out of range by -555,
i.e. -5.55 %) instead of letting it pass.
Both bugs date back to v5.4. 64-bit platforms are not affected.
Tool use (see Documentation/process/generated-content.rst): both
patches, their changelogs and this cover letter were prepared with an
LLM coding assistant (Claude Code), which traced the wrong clock rates
I measured on the device to the overflows, wrote the fixes and drafted
the texts. It also recalculated the old and new arithmetic for the
affected rates in a small userspace program; the results match the
rates measured on the device. I reviewed the changes and ran the tests
on the device.
---
Patrick Fischer (2):
serial: tegra: Fix overflow in tegra_get_tolerance_rate()
serial: tegra: Fix overflow in tegra_check_rate_in_range()
drivers/tty/serial/serial-tegra.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
---
base-commit: 734bef548a96e8774d6eef5dfa2026c6edc4e80b
change-id: 20261023-upstream-serial-tegra-overflow-48d3d0f7afd9
Best regards,
--
Patrick Fischer <admin@xxxxxxxxxxxxxxxxxx>