Re: [PATCH v2] iommu/arm-smmu-v3: Align memory attributes for SMMU-originated accesses

[Daniel Mentz]

On Fri, Oct 16, 2026 at 11:05 AM Jason Gunthorpe <jgg@xxxxxxxx> wrote:
> On Sun, Oct 04, 2026 at 07:50:27PM +0000, Daniel Mentz wrote:
> > The SMMU specification defines several types of SMMU-originated memory
> > accesses, including Stage 1 and Stage 2 translation table walks, stream
> > table accesses (L1STD and STE fetches), CD table accesses (L1CD and CD
> > fetches), and queue accesses (CMDQ fetch, EVENTQ write, PRIQ write).
> >
> > While the memory attributes used for Stage 1 and Stage 2 translation
> > table walks are configured in io-pgtable-arm based on whether the SMMU
> > is coherent (ARM_SMMU_FEAT_COHERENCY), the attributes for stream tables,
> > CD tables, and queues are currently hardcoded to Inner Shareable,
> > Write-Back.
> >
> > On non-coherent systems, however, memory for stream tables, CD tables,
> > and queues is allocated via dma_alloc_coherent() /
> > dmam_alloc_coherent(), which provides CPU mappings with Normal
> > Non-Cacheable attributes. Having a non-coherent SMMU access these
> > buffers with Inner Shareable, Write-Back attributes results in
> > mismatched memory attributes between the CPU and the SMMU.
> >
> > Configure the memory attributes for tables and queues in
> > arm_smmu_device_reset() and arm_smmu_make_cdtable_ste() based on
> > ARM_SMMU_FEAT_COHERENCY, matching the attributes used for translation
> > table walks:
> >
> > - In SMMU_CR1, use Outer Shareable, Non-Cacheable for non-coherent
> >   SMMUs, while retaining Inner Shareable, Write-Back for coherent SMMUs.
> >   This applies to stream table accesses as well as queue accesses (CMDQ
> >   fetch, EVENTQ write, PRIQ write).
> > - In STE.{S1CIR, S1COR, S1CSH}, use Outer Shareable, Non-Cacheable for
> >   non-coherent SMMUs, while retaining Inner Shareable, Write-Back
> >   Read-Allocate for coherent SMMUs. This applies to CD table accesses.
> >
> > Assisted-by: LLM
> > Reviewed-by: Nicolin Chen <nicolinc@xxxxxxxxxx>
> > Signed-off-by: Daniel Mentz <danielmentz@xxxxxxxxxx>
> > ---
> > Changes in v2:
> > - Rename local variables 'cache' and 'sh' to 'cr1_cache' and 'cr1_sh' in
> >   arm_smmu_device_reset() (Nicolin, Will)
> > - Collect Reviewed-by from Nicolin
> > - Link to v1: https://lore.kernel.org/linux-iommu/20260929032229.3532247-1-danielmentz@xxxxxxxxxx/
> >
> >  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 37 +++++++++++++++------
> >  1 file changed, 27 insertions(+), 10 deletions(-)
>
> I think this looks OK
>
> Reviewed-by: Jason Gunthorpe <jgg@xxxxxxxxxx>
>
> Did you check the spec that this is every access? I remember there is
> a table outlining every access and where the memory attribute lives?

Hi Jason,

Thanks for the review!

I checked section 13.8 ("Attributes for SMMU-originated accesses") in
the SMMUv3 spec (ARM IHI 0070), and all other accesses are already
covered:

- STE fetches (SMMU_CR1.TABLE_*) and Queue accesses
  (SMMU_CR1.QUEUE_*): updated by this patch.
- CD fetches (STE.{S1CIR, S1COR, S1CSH}): updated by this patch.
- Stage 1 and Stage 2 translation table walks (CD.{IR0, OR0, SH0} and
  STE.{S2IR0, S2OR0, S2SH0}): already handled by io-pgtable-arm
- VMS fetches: governed by SMMU_CR1.TABLE_* (and not used by the
  driver).
- Event queue, PRI queue, and GERROR MSIs (*_IRQ_CFG2):
  arm_smmu_write_msi_msg() already programs these to
  Device-nGnRE since they target an interrupt controller.
- CMD_SYNC MSIs (CMD_SYNC.{MSIAttr, MSH}): the driver only uses
  CMD_SYNC MSIs (CS_IRQ) when ARM_SMMU_OPT_MSIPOLL is set, and
  arm_smmu_device_hw_probe() only enables ARM_SMMU_OPT_MSIPOLL when
  coherent is true. When non-coherent, CS_SEV (or CS_NONE) is used and
  MSIAttr/MSH are ignored.

Daniel