Re: [PATCH 1/2] dt-bindings: clocks: qcom,gcc-ipq8074: allow CMN PLL bias clocks

[Krzysztof Kozlowski]

On Sat, Oct 24, 2026 at 12:33:09PM +0200, Robert Marko wrote:
> CMN PLL in IPQ8074 provides 2 fixed clocks to the GCC clock controller.
> In order to describe this in DTS, allow passing them as the inputs to GCC.
> 
> This has a benefit that it avoids doing a global matching by name.

That's ABI break, so at minItems.

> 
> Signed-off-by: Robert Marko <robimarko@xxxxxxxxx>
> ---
>  Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
> index 00d7df75b3d6..d489c6332e6c 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
> @@ -29,6 +29,8 @@ properties:
>        - description: sleep clock
>        - description: Gen3 QMP PCIe PHY PIPE clock
>        - description: Gen2 QMP PCIe PHY PIPE clock
> +      - description: 300 MHz bias clock from CMN PLL
> +      - description: 416.5 MHz NSS NoC bias clock from CMN PLL
>  
>    clock-names:
>      items:
> @@ -36,6 +38,8 @@ properties:
>        - const: sleep_clk
>        - const: pcie0_pipe
>        - const: pcie1_pipe
> +      - const: bias_pll_cc_clk
> +      - const: bias_pll_nss_noc_clk

Drop _clk. Names should represent the input.

Best regards,
Krzysztof