[PATCH v2 0/7] i3c: renesas: Add RZ/G3L support

[Diogo Ivo]

Hi,

this series adds I3C support for the Renesas RZ/G3L (R9A08G046) SoC and
enables the controller on the RZ/G3L SMARC EVK.

It starts with a driver fix, which is independently applicable and
marked for stable: on a pure I3C bus, the I3C core leaves the I2C SCL
rate at zero, and the driver used to derive a zero-width open-drain SCL
from it. It now falls back to the 1 MHz FM+ limit instead. There is also
a small cosmetic patch removing a comma after the sentinel in the
compatible table, for consistency.

The rest of the series adds the DT bindings, the CPG clocks and resets,
and the SoC and board device tree support for RZ/G3L. The driver only
consumes resources that are common to the RZ/G3L and the RZ/G3S
(R9A08G045) (the tclk clock, the presetn and tresetn resets and seven
named interrupts), so no driver changes are needed: the RZ/G3L is
described by the SoC-specific renesas,r9a08g046-i3c compatible with a
fallback to the renesas,r9a08g045-i3c compatible of the RZ/G3S, which
the driver already matches.

The board enablement is guarded by the SW_I3C_EN switch, as the pins
are shared with RIIC3 and the audio codec behind it.

The I3C I/O voltage can be set to 1.2V or 1.8V on the board through
the SYS.3 (I3C_IOVS) switch. As software needs to tell the pin
controller which voltage is in effect, the series also adds pin
controller support for the I3C power source on RZ/G3L together with the
matching board device tree configuration.

Signed-off-by: Diogo Ivo <diogo.ivo.sx@xxxxxxxxxxx>
---
Changes in v2:
- Drop the "i3c: renesas: Add RZ/G3L support" patch and express the
  compatibility of the RZ/G3L with a fallback to the
  renesas,r9a08g045-i3c compatible in the bindings and in the DTS, as
  suggested by Krzysztof.
- Split the clock and interrupt constraints in the bindings into
  separate if/else blocks to handle the RZ/G3S fallback on RZ/G3L
  nodes.
- Sort the &i3c and i3c_pins nodes alphabetically in
  r9a08g046l48-smarc.dts.
- Link to v1: https://patch.msgid.link/20261020-divo-ssgrlpcsrc-2966-i3c-v1-0-30a47f25e515@xxxxxxxxxxx

---
Diogo Ivo (7):
      i3c: renesas: Fix zero I2C SCL rate on pure I3C buses
      i3c: renesas: Drop comma after OF match table sentinel
      dt-bindings: i3c: renesas,i3c: Add RZ/G3L support
      clk: renesas: r9a08g046: Add I3C clocks and resets
      pinctrl: renesas: rzg2l: Split SoC-specific masks in struct rzg2l_register_masks
      pinctrl: renesas: rzg2l: Add RZ/G3L support for selecting I3C power source
      arm64: dts: renesas: r9a08g046: Add I3C support

 .../devicetree/bindings/i3c/renesas,i3c.yaml       | 27 +++++++++++------
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi         | 35 ++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts | 21 +++++++++++++
 arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi   |  4 +++
 drivers/clk/renesas/r9a08g046-cpg.c                |  7 +++++
 drivers/i3c/master/renesas-i3c.c                   | 12 ++++++--
 drivers/pinctrl/renesas/pinctrl-rzg2l.c            | 25 ++++++++--------
 7 files changed, 107 insertions(+), 24 deletions(-)
---
base-commit: 5d13f5297a1bd1fdff5fab7efcdbc9bfe407e457
change-id: 20261020-divo-ssgrlpcsrc-2966-i3c-bca85b48f943

Best regards,
--  
Diogo Ivo <diogo.ivo.sx@xxxxxxxxxxx>