[PATCH] arm64: dts: rockchip: Add the watchdog reset to RK3399

[Igor Velkov via B4 Relay]

From: Igor Velkov <iav@xxxxxx>

The RK3399 watchdog at 0xff848000 is reset by SRST_P_WDT0 (bit 5 of
CRU_SOFTRST_CON20), but its node has no resets property. Its clock is
gated from SECURE_GRF_SOC_CON3[8], out of reach for Linux, so without
the reset dw_wdt_stop() can only set WDOG_HW_RUNNING and the watchdog
keeps counting through s2idle: on a Kobol Helios64 and a ROCK Pi 4A,
s2idle longer than the watchdog timeout ends in a watchdog reset.

With the reset line dw_wdt_stop() can stop the watchdog, and with
"watchdog: dw_wdt: manage reset line during system suspend/resume" the
driver holds it in reset while the system sleeps.

Signed-off-by: Igor Velkov <iav@xxxxxx>
---
The dw_wdt side is applied in the watchdog tree:
https://lore.kernel.org/r/20261024140854.25664-3-a.shimko.dev@xxxxxxxxx
---
 arch/arm64/boot/dts/rockchip/rk3399-base.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
index c46e58d4af0d..7b71b24c1f51 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
@@ -1748,6 +1748,7 @@ watchdog@ff848000 {
 		reg = <0x0 0xff848000 0x0 0x100>;
 		clocks = <&cru PCLK_WDT>;
 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
+		resets = <&cru SRST_P_WDT0>;
 	};
 
 	rktimer: rktimer@ff850000 {

---
base-commit: d2abcbb905b0e4b2e06b257fa1e5bcf4faa6dbda
change-id: 20261027-rk3399-wdt-reset-c58d2111609d

Best regards,
-- 
Igor Velkov <iav@xxxxxx>