Re: [PATCH v2 3/3] clk: qcom: dprxcc: Add Nord DPRX clock controller support

[Taniya Das]

On 10/15/2026 7:51 PM, Konrad Dybcio wrote:
>> Reviewed-by: Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx>
>> Signed-off-by: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
>> ---
> [...]
> 
>> +	/*
>> +	 * Configure cdiv 20 for core aud and 11 for core ahb clks of DPRX CC
>> +	 */
> Nit: this fits in a /* single-line comment */
> 
>> +	regmap_write(regmap, dprx_1_dprx_cc_core_aud_div_clk_src.reg, 0x13);
>> +	regmap_write(regmap, dprx_1_dprx_cc_core_ahb_div_clk_src.reg, 0x0A);
> Hex should be lowercase, but preferably please define some sort of a bitfield
> that this value is written into and run regmap_update_bits()
> 
> You should also set `.use_rpm = true`

Will fix in the next patch.

-- 
Thanks,
Taniya Das