Re: [PATCH 3/3] drm/amd/display: report synced Apple 5K tiles to PowerPlay for MCLK switch

[Alex Deucher]

On Tue, Oct 27, 2026 at 5:41 AM Richard Lane <richardlanedev@xxxxxxxxx> wrote:
>
> When driving both 2560x2880 tiles of an Apple 5K iMac panel, Display
> Core's program_timing_sync() already aligns both CRTCs in hardware
> during dc_commit_streams() because the two streams share identical
> timings.
>
> However, on DCE < 12 (iMac15,1 through Polaris-based iMac19,1), Display
> Core leaves pp_display_cfg.all_displays_in_sync unset. Because PowerPlay
> is not informed that the two streams have synchronized vertical blanking
> intervals, SMU7 prevents MCLK switching at idle or causes modeset
> underflows.
>
> Report all_displays_in_sync = true to PowerPlay after committing both
> tiled streams so SMU7 knows the tiles blank simultaneously and can
> safely downclock MCLK at idle.
>
> Signed-off-by: Richard Lane <richardlanedev@xxxxxxxxx>
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 548f975c7324..384a81371f80 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4788,6 +4788,19 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_commit *state,
>         mutex_lock(&dm->dc_lock);
>         dc_exit_ips_for_hw_access(dm->dc);
>         WARN_ON(!dc_commit_streams(dm->dc, &params));
> +       /*
> +        * DCE < 12 leaves all_displays_in_sync unset; report synchronized
> +        * Apple 5K tiles to PowerPlay after commit so SMU7 can downclock MCLK
> +        * at idle without modeset underflows.
> +        */
> +       if (params.stream_count == 2 &&
> +           params.streams[0]->link->tiled_peer == params.streams[1]->link) {

This should be made generic for any combination of displays with
identical timings.

Alex

> +               struct dm_pp_display_configuration *pp_cfg =
> +                       &dm->dc->current_state->pp_display_cfg;
> +
> +               pp_cfg->all_displays_in_sync = true;
> +               dm_pp_apply_display_requirements(dm->dc->ctx, pp_cfg);
> +       }
>
>         bool frl_stream_found = false;
>
> --
> 2.55.0