Re: [PATCH v3] PCI: rockchip: Don't lengthen PERST# when power is already valid
From: Shawn Lin
Date: Tue Oct 27 2026 - 22:23:01 EST
在 2026/10/28 星期三 9:59, Enrique Hernández Bello 写道:
On Wed, 28 Oct 2026 09:34:04 +0800, Shawn Lin wrote:
...
Furthermore, even with the same power supply design, different endpoints
may behave differently. What if a particular device requires a longer
reset pulse to work reliably? How would we handle that?
The only floor the spec gives is T_PERST, 100 us of active PERST#, and v4
started guaranteeing that explicitly with an fsleep() rather than relying on
the 100 ms. Beyond that there is no required minimum to preserve.
And the short pulse is not new behaviour: from the driver's introduction
until c47f90be4c89 in v6.11-rc1 there was no wait before the de-assert at
all, so the pulse was only as long as the register writes in between took.
That is what every endpoint on this driver saw for years. The 100 ms pulse
is the recent change, and it is what broke this one. If some device turns
out to need longer, that seems like a quirk for that device rather than a
reason to keep a default that regressed another.
Was it possible to add a DT property for configurable delay? I came
across several EPs need quite a longer wait time, so add it in the
vendor tree for dwc-based IP[1]. That could be applied here to slove
your cases and others', and might avoid regression.
[1] https://github.com/rockchip-linux/kernel/blob/develop-6.12/drivers/pci/controller/dwc/pcie-dw-rockchip.c#L865