Re: [PATCH v2 2/6] iio: adc: ti-ads1298: fix power-up and clock handling
From: Mike Looijmans
Date: Wed Oct 28 2026 - 02:48:46 EST
On 10/28/26 03:19, Stephan Costa Barros wrote:
Hi Mike,Ah, okay.
On Mon, Oct 26, 2026 at 07:27:22AM +0100, Mike Looijmans wrote:
On 25-10-2026 01:13, Stephan Costa Barros wrote:Thanks, that experience is what I lack here.
- The datasheet powers up the supplies first, then the clock, thenThe driver followed the correct procedure: Keep reset asserted until the
waits t_POR = 2^18 clock cycles (128 ms at 2.048 MHz) before the
reset. The driver enabled an external clock and the vref supply
before AVDD, reset right away, and did not wait for the 150 ms
start-up of the internal reference. Follow the datasheet. Probe takes
about 280 ms longer.
power is enabled.
We've seen the chips misbehave when the power supplies ramp up
erratically. Keeping them in reset until the power supplies are stable
solves that issue, if a reset signal is available. The driver is based
on real experience with these chips.
The patch keeps that: RESET is still requested asserted before anything
is enabled, and released only after AVDD, VREF and the clock are on.
What changes is that AVDD now comes before the clock and VREF, and that
the driver waits t_POR before releasing RESET. "reset right away" meant
releasing it without that wait; I'll reword it.
Is AVDD before the clock fine with you? Section 11.1 asks to keep all
digital inputs, CLK included, low until the supplies are stable.
That sounds solid, better than it was.
There is no need to wait for the internal reference startup. TheAgreed, I'll drop that wait.
internal reference only affects the ADC performance, it isn't required
for digital communication. By the time userspace gets to use the driver,
those 150 ms will have passed already.
We actually have 8 (or more) of these chips on a single board. If itUnderstood. Without the reference wait it is t_POR alone, 128 ms per
takes 8x 280 ms extra to boot such a board, it will fail to meet medical
specs (reboot in 5 seconds).
chip at 2.048 MHz, still about 1 s for 8 chips probed one after another.
Which is still unreasonably long.
We modelled this into the power supply.
The 8 chips all share their power supplies, so the first to switch on will need the delay, but the others don't. So if you put a delay on the power supply, only whatever device triggers it first will have to wait. All devices that use that power supply will wait in parallel. And if the supply is on at boot, there'll be no delay.
The ADS1298 datasheet says "18" clock cycles, not "2^18". Quite aI read 2^18 in the current revision, SBAS459K (August 2015), Table 38:
difference. We would definitely have noticed if the reset timeout was
that far off.
"t_POR, Wait after power up until reset, MIN 2^18 t_CLK", with the note
"When using an external clock, t_POR timing does not start until CLK is
valid". Its revision history lists "Changed power-up reset wait time in
Table 38", so older revisions may differ. The 18 t_CLK in Figure 105 is
the wait after the reset pulse, which the driver already does. The
ADS1299 datasheet (SBAS499C, Table 30) gives 2^18 t_CLK as well.
Oh, you're quite right, I stand corrected. Don't recall it, it's been a while since I worked on that project.
That said, I have not seen the missing wait cause a failure on hardware.
On my board the supplies are up long before the driver probes, so t_POR
has passed by then, and that may be the case on yours too. Does the
driver switch the supplies on your boards, or are they on from boot?
The AVDD is separate and shared, the DVDD is just always on (also powers the CPU and a bunch of IO banks).
But what I said before applies, the delay should be in the power supply. Then all devices sharing that supply can wait in parallel.
In v3 the supply order, the t_POR wait and the clock rate become
separate patches, as Jonathan asked, so each can be judged on its own.
Regards,
Stephan
Mike.