[PATCH v2 1/5] spi: dw: Detect DDR support in enhanced SPI mode

[Changhuang Liang]

DDR (Dual Data-Rate) is a synthesis option of the DW SSI IP, separate
from the enhanced SPI mode. When it is not implemented, the
SPI_CTRLR0.SPI_DDR_EN bit reads back as zero.

Check whether SPI_DDR_EN is writable in detect_enh_mode(), the same
way clock stretching is checked, and record the result in a new
DW_SPI_CAP_DDR capability. A follow-up patch uses it to decide
whether DTR operations can be advertised to the spi-mem layer.

Signed-off-by: Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
---
 drivers/spi/spi-dw-core.c | 12 +++++++++---
 drivers/spi/spi-dw.h      |  2 ++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index 47434fa78e4b..e8f70808352a 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -1269,9 +1269,11 @@ static u16 detect_enh_mode(struct dw_spi *dws)
 		goto disable_enh;
 
 	/* test clock stretching */
-	dw_writel(dws, DW_SPI_SPI_CTRLR0, DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN);
-	if ((DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN & dw_readl(dws, DW_SPI_SPI_CTRLR0)) !=
-	    DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN) {
+	dw_writel(dws, DW_SPI_SPI_CTRLR0,
+		  DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN | DW_SPI_ENH_CTRLR0_SPI_DDR_EN);
+
+	tmp_val = dw_readl(dws, DW_SPI_SPI_CTRLR0);
+	if (!(tmp_val & DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN)) {
 		/*
 		 * If clock stretching is not enabled then do not use
 		 * enhanced mode.
@@ -1282,6 +1284,10 @@ static u16 detect_enh_mode(struct dw_spi *dws)
 
 	dws->caps |= DW_SPI_CAP_EMODE;
 
+	/* test DDR support, SPI_DDR_EN is read-only zero if not implemented */
+	if (tmp_val & DW_SPI_ENH_CTRLR0_SPI_DDR_EN)
+		dws->caps |= DW_SPI_CAP_DDR;
+
 disable_enh:
 	dw_writel(dws, DW_SPI_CTRLR0, tmp_ctrlr0);
 	dw_writel(dws, DW_SPI_SPI_CTRLR0, tmp_spi_ctrlr0);
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index c16225c5c887..f922e000e7a0 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -36,6 +36,7 @@
 #define DW_SPI_CAP_CS_OVERRIDE		BIT(0)
 #define DW_SPI_CAP_DFS32		BIT(1)
 #define DW_SPI_CAP_EMODE		BIT(2)
+#define DW_SPI_CAP_DDR			BIT(3)
 
 /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
 #define DW_SPI_CTRLR0			0x00
@@ -139,6 +140,7 @@
 
 /* Bit fields in SPI_CTRLR0 */
 #define DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN	BIT(30)
+#define DW_SPI_ENH_CTRLR0_SPI_DDR_EN		BIT(16)
 #define DW_SPI_ENH_CTRLR0_WAIT_CYCLE_MASK	GENMASK(15, 11)
 #define DW_SPI_ENH_CTRLR0_INST_L_MASK		GENMASK(9, 8)
 #define DW_SPI_ENH_CTRLR0_INST_L_INST_L0	0x0
-- 
2.25.1