[PATCH v2 2/4] clk: ti: fapll: Fix clock speed calculation
From: Ettore Chimenti
Date: Wed Oct 28 2026 - 11:55:37 EST
From: Andrew Goodbody <andrew.goodbody@xxxxxxxxxx>
The fractional part of the divider was being treated as 1/10000000
whereas it is in fact 1/2^24 (1/16777216). This led to incorrect clock
speeds being reported when a fractional divider was in use. Correct it.
As well as fixing the clock speed calculation when read, also update the
calculation on set in a similar manner.
Fixes: 163152cbbe32 ("clk: ti: Add support for FAPLL on dm816x")
Signed-off-by: Andrew Goodbody <andrew.goodbody@xxxxxxxxxx>
Signed-off-by: Ettore Chimenti <ettore.chimenti@xxxxxxxxxx>
---
drivers/clk/ti/fapll.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index ae2f6fed10f6..8ab9acd57b60 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -336,8 +336,8 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
v = readl_relaxed(synth->freq);
synth_int_div = (v >> 24) & 0xf;
synth_frac_div = v & 0xffffff;
- synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
- rate *= 10000000;
+ synth_div_freq = (synth_int_div * 16777216) + synth_frac_div;
+ rate *= 16777216;
do_div(rate, synth_div_freq);
rate *= SYNTH_PHASE_K;
}
@@ -378,10 +378,10 @@ static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth,
for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) {
synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate *
SYNTH_PHASE_K *
- 10000000,
+ 16777216,
rate * post_div_m);
- synth_frac_div = synth_int_div % 10000000;
- synth_int_div /= 10000000;
+ synth_frac_div = synth_int_div % 16777216;
+ synth_int_div /= 16777216;
if (synth_int_div <= SYNTH_MAX_INT_DIV)
break;
--
2.56.0