[PATCH 1/4] dt-bindings: interrupt-controller: add Mobileye EyeQ5 PCIe MSI controller

[Gregory CLEMENT]

Add binding for the Mobileye EyeQ5 PCIe MSI controller.

Signed-off-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxx>
---
 .../interrupt-controller/mobileye,eyeq5-msi.yaml   | 120 +++++++++++++++++++++
 1 file changed, 120 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mobileye,eyeq5-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/mobileye,eyeq5-msi.yaml
new file mode 100644
index 0000000000000..919af55fc8a60
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mobileye,eyeq5-msi.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mobileye,eyeq5-msi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobileye EyeQ5 PCIe MSI controller
+
+maintainers:
+  - Gregory CLEMENT <gregory.clement@xxxxxxxxxxx>
+
+description: |
+  The Mobileye EyeQ5 PCIe MSI controller snoops the MSI write TLPs of a
+  PCIe port. The controller signals the parent interrupt controller when a
+  vector is pending. The memory-region property gives the base address of
+  the doorbell window. A port supports a maximum of 4 MSI vectors.
+
+  This node is both an MSI parent for the PCIe port and a chained interrupt
+  controller.
+
+allOf:
+  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
+
+properties:
+  compatible:
+    const: mobileye,eyeq5-msi
+
+  reg:
+    items:
+      - description: GCSR block of the PCIe port
+      - description: MSI vector control block
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 1
+
+  msi-controller: true
+
+  '#msi-cells':
+    const: 0
+
+  label:
+    $ref: /schemas/types.yaml#/definitions/string
+    description: Name of the MSI domain. If omitted, the node name is used.
+
+  memory-region:
+    maxItems: 1
+    description:
+      Reserved-memory region. The hardware uses its base address as the MSI
+      doorbell window.
+
+  num-vectors:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Number of MSI vectors that the port supports.
+    minimum: 1
+    maximum: 4
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-controller
+  - '#interrupt-cells'
+  - msi-controller
+  - '#msi-cells'
+  - memory-region
+  - num-vectors
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    / {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        gic: interrupt-controller {
+            compatible = "mti,cpu-interrupt-controller";
+            interrupt-controller;
+            #interrupt-cells = <3>;
+        };
+
+        reserved-memory {
+            #address-cells = <2>;
+            #size-cells = <2>;
+            ranges;
+
+            pci0_msi_reserved: pci0-msi@806000000 {
+                reg = <0x8 0x06000000 0x0 0x100000>;
+            };
+        };
+
+        soc {
+            #address-cells = <2>;
+            #size-cells = <2>;
+            ranges;
+
+            msi0: msi-controller@5840000 {
+                compatible = "mobileye,eyeq5-msi";
+                reg = <0x0 0x05840000 0x0 0x10>,
+                      <0x0 0x05840040 0x0 0x20>;
+                label = "port0-msi";
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                msi-controller;
+                #msi-cells = <0>;
+                memory-region = <&pci0_msi_reserved>;
+                num-vectors = <4>;
+            };
+        };
+    };

-- 
2.53.0