[PATCH v2 3/3] drm/amd/display: report synced displays to PowerPlay for MCLK switch

[Richard Lane]

When driving multiple displays or tiled panels with identical timings
(such as the two 2560x2880 tiles of an Apple 5K iMac panel), Display
Core's program_timing_sync() aligns the CRTCs into a timing sync group
in hardware during dc_commit_streams().

However, on DCE < 12, Display Core leaves
pp_display_cfg.all_displays_in_sync unset. Because PowerPlay is not
informed that the streams have synchronized vertical blanking intervals,
SMU7 prevents MCLK switching at idle or causes modeset underflows.

If all active streams belong to the same timing sync group
(timing_sync_info.group_size == params.stream_count), report
all_displays_in_sync = true to PowerPlay after committing the streams so
SMU7 can safely downclock MCLK at idle.

Signed-off-by: Richard Lane <richardlanedev@xxxxxxxxx>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 74cd88d8d580..b4531383437e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4777,6 +4777,16 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_commit *state,
 	dc_exit_ips_for_hw_access(dm->dc);
 	WARN_ON(!dc_commit_streams(dm->dc, &params));
 
+	if (params.stream_count > 1 &&
+	    dm->dc->current_state->stream_status[0].timing_sync_info.group_size ==
+	    params.stream_count) {
+		struct dm_pp_display_configuration *pp_cfg =
+			&dm->dc->current_state->pp_display_cfg;
+
+		pp_cfg->all_displays_in_sync = true;
+		dm_pp_apply_display_requirements(dm->dc->ctx, pp_cfg);
+	}
+
 	bool frl_stream_found = false;
 
 	for (i = 0; i < params.stream_count; i++) {
-- 
2.55.0