Re: [PATCH v6 07/15] drm/msm/a8xx: Stop getting GMEM_PROTECT from nonctx list
From: Akhil P Oommen
Date: Thu Nov 05 2026 - 17:02:53 EST
On 11/6/2026 1:59 AM, Rob Clark wrote:
> We can just simplify things and calculate the value, instead of manually
> adding it to the nonctx list.
>
> Tested-by: Alexander Koskovich <akoskovich@xxxxx> # Milos (Nothing Phone 3a)
> Signed-off-by: Rob Clark <robin.clark@xxxxxxxxxxxxxxxx>
Reviewed-by: Akhil P Oommen <akhilpo@xxxxxxxxxxxxxxxx>
-Akhil
> ---
> drivers/gpu/drm/msm/adreno/a8xx_catalog.c | 6 ------
> drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 12 ++++--------
> 2 files changed, 4 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a8xx_catalog.c b/drivers/gpu/drm/msm/adreno/a8xx_catalog.c
> index dd1a5ca91812..6c5ee227243a 100644
> --- a/drivers/gpu/drm/msm/adreno/a8xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a8xx_catalog.c
> @@ -27,7 +27,6 @@ static const struct adreno_reglist_pipe a830_nonctxt_regs[] = {
> { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
> /* Partially enable perf clear, Disable DINT to c/z be data forwarding */
> { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) },
> - { REG_A8XX_RB_GC_GMEM_PROTECT, 0x0c000000, BIT(PIPE_BR) },
> /* Configure number of outstanding transactions to 32 */
> { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
> /* Configure UCHE request time out to 16 cycles for CCU/UCHE arbitration */
> @@ -309,7 +308,6 @@ static const struct adreno_reglist_pipe x285_nonctxt_regs[] = {
> { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
> { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
> { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
> - { REG_A8XX_RB_GC_GMEM_PROTECT, 0x15000000, BIT(PIPE_BR) },
> { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
> { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
> { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
> @@ -483,7 +481,6 @@ static const struct adreno_reglist_pipe a810_nonctxt_regs[] = {
> { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
> { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00100020, BIT(PIPE_BV) | BIT(PIPE_BR) },
> { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
> - { REG_A8XX_RB_GC_GMEM_PROTECT, 0x00900000, BIT(PIPE_BR) },
> { },
> };
>
> @@ -709,7 +706,6 @@ static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
> { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
> /* Partially enable perf clear, Disable DINT to c/z be data forwarding */
> { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) },
> - { REG_A8XX_RB_GC_GMEM_PROTECT, 0x12000000, BIT(PIPE_BR) },
> { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
> { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
> { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
> @@ -1102,7 +1098,6 @@ static const struct adreno_reglist_pipe a845_nonctxt_regs[] = {
> { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
> { REG_A7XX_RB_CCU_DBG_ECO_CNTL, BIT(10) | BIT(9), BIT(PIPE_BR) },
> { REG_A6XX_RB_DBG_ECO_CNTL, BIT(17), BIT(PIPE_BV) | BIT(PIPE_BR) },
> - { REG_A8XX_RB_GC_GMEM_PROTECT, 0x0C000000, BIT(PIPE_BR) },
> { REG_A6XX_RB_RBP_CNTL, BIT(5) | BIT(6), BIT(PIPE_BV) | BIT(PIPE_BR) },
> { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
> { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
> @@ -1161,7 +1156,6 @@ static const struct adreno_reglist_pipe a850_nonctxt_regs[] = {
> { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
> { REG_A7XX_RB_CCU_DBG_ECO_CNTL, BIT(10) | BIT(9), BIT(PIPE_BR) },
> { REG_A6XX_RB_DBG_ECO_CNTL, BIT(17), BIT(PIPE_BV) | BIT(PIPE_BR) },
> - { REG_A8XX_RB_GC_GMEM_PROTECT, 0x12000000, BIT(PIPE_BR) },
> { REG_A6XX_RB_RBP_CNTL, BIT(5) | BIT(6), BIT(PIPE_BV) | BIT(PIPE_BR) },
> { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
> { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
> diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> index 59898b49a201..f65bf82e5c21 100644
> --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> @@ -370,7 +370,7 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu)
> hbb_lo << 1 | ubwc_mode);
> }
>
> -static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect)
> +static void a8xx_nonctxt_config(struct msm_gpu *gpu)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> struct a6xx_gmu *gmu = &to_a6xx_gpu(adreno_gpu)->gmu;
> @@ -390,9 +390,6 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect)
> if (!(BIT(pipe_id) & regs[i].pipe))
> continue;
>
> - if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT)
> - *gmem_protect = regs[i].value;
> -
> if ((regs[i].offset << 2) >= gmu->mmio_offset) {
> gmu_write(gmu, regs[i].offset, regs[i].value);
> } else {
> @@ -638,7 +635,6 @@ static int hw_init(struct msm_gpu *gpu)
> struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
> unsigned int pipe_id, i;
> - u32 gmem_protect = 0;
> u64 gmem_range_min;
> int ret;
>
> @@ -719,7 +715,7 @@ static int hw_init(struct msm_gpu *gpu)
>
> gpu_write(gpu, REG_A8XX_UCHE_CLIENT_PF, BIT(7) | 0x1);
>
> - a8xx_nonctxt_config(gpu, &gmem_protect);
> + a8xx_nonctxt_config(gpu);
>
> /* Enable fault detection */
> gpu_write(gpu, REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, BIT(30) | 0xcfffff);
> @@ -838,8 +834,8 @@ static int hw_init(struct msm_gpu *gpu)
> * GMEM_PROTECT register should be programmed after GPU is transitioned to
> * non-secure mode
> */
> - a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_GC_GMEM_PROTECT, gmem_protect);
> - WARN_ON(!gmem_protect);
> + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_GC_GMEM_PROTECT,
> + (adreno_gpu->info->gmem / SZ_4K) << 16);
> a8xx_aperture_clear(gpu);
>
> if (!a6xx_gpu->pwrup_reglist_emitted) {