Re: [PATCH] MIPS: mm: Fix the cache error vector jump for XKPHYS kernels

[Maciej W. Rozycki]

On Wed, 21 Oct 2026, Imre Kaloz wrote:

> diff --git a/arch/mips/mm/cex-gen.S b/arch/mips/mm/cex-gen.S
> index e528583d1331..6989fe274aab 100644
> --- a/arch/mips/mm/cex-gen.S
> +++ b/arch/mips/mm/cex-gen.S
> @@ -37,6 +38,21 @@
>  	nop
>  	nop
>  
> +#if defined(CONFIG_64BIT) && VMLINUX_LOAD_ADDRESS >= XKPHYS && \
> +    VMLINUX_LOAD_ADDRESS < XKSEG

 Not VMLINUX_LOAD_ADDRESS < CKSEG0 to take care of CONFIG_MAPPED_KERNEL?
Of course we'd have to switch caching in the wired TLB entry then too, but 
at least we won't crash outright...

> +	/*
> +	 * An XKPHYS kernel may lie outside the 256MB region a j from the
> +	 * vector reaches, so jump to the handler's uncached XKPHYS address.
> +	 */
> +	PTR_LA	k0, cache_parity_error
> +	PTR_LI	k1, TO_PHYS_MASK
> +	and	k0, k0, k1
> +	PTR_LI	k1, UNCAC_BASE
> +	or	k0, k0, k1
> +	jr	k0
> +	nop

 Given that this runs at ERL, a much shorter sequence could look like:

	LEAF(except_vec2_generic)
0:
	[...]
	PTR_L	k0, %lo(0x100 + (1f - 0b))(zero)
	jr	k0
	 nop
1:
	.quad	cache_parity_error
	[...]
	END(except_vec2_generic)

but I guess it doesn't matter that much as long as we don't overrun the 
exception handler slot, since this is obviously not a hot path.  Still it 
could be considered neater, couldn't it?

  Maciej