[PATCH v3 5/7] media: qcom: camss: Add support for SM8150
From: Andrew Gigena via B4 Relay
Date: Fri Nov 06 2026 - 13:42:20 EST
From: Andrew Gigena <mail@xxxxxxxxxxxxxxxx>
Add CAMSS platform data for the Qualcomm SM8150 SoC. The camera
subsystem contains four CSIPHY, four CSID (two full and two lite), two
VFE and two VFE-Lite instances.
The hardware reuses the existing 3-phase 1.0 CSIPHY, Gen2 CSID and
VFE 17x implementations; the CSIPHY uses the SC8280XP lane register
layout. Add CAMSS_8150 to the version enum and to the shared code
paths, then add the per-block clock, regulator, power domain,
interrupt and interconnect resources.
The CSIPHY resources are reduced to id/hw_ops/formats only; clocks,
regulators, registers and interrupts are owned by the dedicated CSI2
PHY driver.
Signed-off-by: Andrew Gigena <mail@xxxxxxxxxxxxxxxx>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 2 +
drivers/media/platform/qcom/camss/camss.c | 231 +++++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
3 files changed, 234 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index dac8d2ecf799..5e7c2e67ae88 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -1133,6 +1133,7 @@ static bool csiphy_is_gen2(u32 version)
case CAMSS_6150:
case CAMSS_6350:
case CAMSS_7280:
+ case CAMSS_8150:
case CAMSS_8250:
case CAMSS_8280XP:
case CAMSS_8300:
@@ -1235,6 +1236,7 @@ static int csiphy_init(struct csiphy_device *csiphy)
regs->lane_regs = &lane_regs_sm8250[0];
regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
break;
+ case CAMSS_8150:
case CAMSS_8280XP:
regs->lane_regs = &lane_regs_sc8280xp[0];
regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index c54185c93a8a..da4d2213fd3d 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -1940,6 +1940,223 @@ static const struct resources_icc icc_res_sm6350[] = {
},
};
+static const struct camss_subdev_resources csiphy_res_sm8150[] = {
+ /* CSIPHY0 - clocks/regs/supplies owned by PHY driver */
+ {
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY1 - clocks/regs/supplies owned by PHY driver */
+ {
+ .csiphy = {
+ .id = 1,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY2 - clocks/regs/supplies owned by PHY driver */
+ {
+ .csiphy = {
+ .id = 2,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY3 - clocks/regs/supplies owned by PHY driver */
+ {
+ .csiphy = {
+ .id = 3,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+};
+
+static const struct camss_subdev_resources csid_res_sm8150[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+ .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_axi" },
+ .clock_rate = { { 400000000, 480000000, 600000000 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .regulators = {},
+ .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_axi" },
+ .clock_rate = { { 400000000, 480000000, 600000000 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE0 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" },
+ .clock_rate = { { 400000000, 480000000, 600000000 },
+ { 0 },
+ { 0 }, },
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE1 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" },
+ .clock_rate = { { 400000000, 480000000, 600000000 },
+ { 0 },
+ { 0 }, },
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ }
+};
+
+/*
+ * cpas_ahb is left at the CAMCC default 80 MHz; it is not matched by
+ * vfe_match_clock_names(). The VFE/VFE-Lite rates are set from the
+ * remaining clock-rate tables.
+ */
+static const struct camss_subdev_resources vfe_res_sm8150[] = {
+ /* VFE0 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi",
+ "vfe0", "vfe0_axi" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
+ { 400000000, 558000000, 637000000, 847000000, 950000000 },
+ { 0 }, },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi",
+ "vfe1", "vfe1_axi" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
+ { 400000000, 558000000, 637000000, 847000000, 950000000 },
+ { 0 }, },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE_0 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_lite0" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
+ { 320000000, 400000000, 480000000, 600000000 }, },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .is_lite = true,
+ .line_num = 4,
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE_1 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_lite1" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
+ { 320000000, 400000000, 480000000, 600000000 }, },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .is_lite = true,
+ .line_num = 4,
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ }
+};
+
+static const struct resources_icc icc_res_sm8150[] = {
+ {
+ .name = "cam_ahb",
+ .icc_bw_tbl.avg = 38400,
+ .icc_bw_tbl.peak = 76800,
+ },
+ {
+ .name = "cam_hf_0_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+ {
+ .name = "cam_hf_1_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+ {
+ .name = "cam_sf_0_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_8250[] = {
/* CSIPHY0 */
{
@@ -5725,6 +5942,19 @@ static const struct camss_resources sm6350_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_sm6350),
};
+static const struct camss_resources sm8150_resources = {
+ .version = CAMSS_8150,
+ .pd_name = "top",
+ .csiphy_res = csiphy_res_sm8150,
+ .csid_res = csid_res_sm8150,
+ .vfe_res = vfe_res_sm8150,
+ .icc_res = icc_res_sm8150,
+ .icc_path_num = ARRAY_SIZE(icc_res_sm8150),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_sm8150),
+ .csid_num = ARRAY_SIZE(csid_res_sm8150),
+ .vfe_num = ARRAY_SIZE(vfe_res_sm8150),
+};
+
static const struct camss_resources sm8250_resources = {
.version = CAMSS_8250,
.pd_name = "top",
@@ -5824,6 +6054,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
{ .compatible = "qcom,sm6150-camss", .data = &sm6150_resources },
{ .compatible = "qcom,sm6350-camss", .data = &sm6350_resources },
+ { .compatible = "qcom,sm8150-camss", .data = &sm8150_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 7dc2fd9f03e0..74d8cc2921be 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -89,6 +89,7 @@ enum camss_version {
CAMSS_8x39,
CAMSS_8x53,
CAMSS_8x96,
+ CAMSS_8150,
CAMSS_8250,
CAMSS_8280XP,
CAMSS_8300,
--
2.56.0