[PATCH] soundwire: qcom: enable CPU interrupts only for MMIO controllers

[Ivan Verbovoy via B4 Relay]

From: Ivan Verbovoy <ivanverbovoy@xxxxxxxxx>

Commit b27be5a85ed3 ("soundwire: qcom: add EE-aware register layout for
Shikra") dropped the ctrl->mmio check around the CPU interrupt enable in
qcom_swrm_init(), which its message does not mention. The enable has
been written for MMIO controllers only since they were added in
commit 82f5c70c2651 ("soundwire: qcom: add support for mmio soundwire
master devices"); a controller inside a codec, reached over SLIMbus, was
left alone.

On a Surface Duo (SM8150, a WCD9340 with one WSA8815 on its SoundWire)
the amplifier no longer enumerates since: "SWR bus clsh detected" at
boot, "link failed to connect" at each resume, and every stream fails
with -110. With the check back it enumerates and plays again. Shikra's
controller is MMIO and keeps the enable.

Fixes: b27be5a85ed3 ("soundwire: qcom: add EE-aware register layout for Shikra")
Signed-off-by: Ivan Verbovoy <ivanverbovoy@xxxxxxxxx>
---
 drivers/soundwire/qcom.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
index 147e55b7a600..99c1b6398894 100644
--- a/drivers/soundwire/qcom.c
+++ b/drivers/soundwire/qcom.c
@@ -995,8 +995,9 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
 			0xFFFFFFFF);
 
 	/* enable CPU IRQs for the selected EE window */
-	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
-			SWRM_INTERRUPT_STATUS_RMSK);
+	if (ctrl->mmio)
+		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
+				SWRM_INTERRUPT_STATUS_RMSK);
 
 	/* Set IRQ to PULSE */
 	ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,

---
base-commit: ddfe51b0a0f5dc9e415cc2c8ad8db17532dd426b
change-id: 20261109-swrm-mmio-irq-d896783a54da

Best regards,
--  
Ivan Verbovoy <ivanverbovoy@xxxxxxxxx>