[PATCH v4 01/13] dt-bindings: clock: renesas,r8a78000-cpg: Add CPG_SGDn_VIO_DP_{TX,OTHER}

[Paul Elder]

Add the CPG_SGDn_VIO_DP_TX and CPG_SGDn_VIO_DP_OTHER clocks that are
used by FCPV, VSP, VCON, and DPTX cores.

It should be noted that there is likely a discrepancy regarding the
clocks. In practice it ought not to be an issue as all the clocks derive
from the same SGD1_VIO_MAIN clock and none of them are programmable or
gateable.

According to the datasheet, the FCPV[BID] and VSPD cores use
SGD*_VIO_DP_TXφ while the VSP[BI] cores use SGD*_VIO_DP_OTHERφ.
However, educated guessing suggests that IP cores in the same pipeline
should be using the same clocks:
- FCPV[BI] -> VSP[BI]:                  SGD*_VIO_DP_OTHERφ
- FCPVD -> VSPD -> VCON -> DPTX:        SGD*_VIO_DP_TXφ

Signed-off-by: Paul Elder <paul.elder+renesas@xxxxxxxxxxxxxxxx>

---
Changes in v4:
- Add all the clocks
- remove DNI
- add notes about suspected clock naming
---
 include/dt-bindings/clock/renesas,r8a78000-cpg.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
index 9d7f3afcb2c52ec4caac574b75810822ad3d59c4..0b2822785a669d99fc0724852e39ec7aa56839ea 100644
--- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h
+++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
@@ -32,5 +32,15 @@
 #define R8A78000_CPG_SGASYNCD16_PERW_MAIN	22
 #define R8A78000_CPG_S0ASYNCD8_PERW_MAIN	23
 #define R8A78000_CPG_CANFD_SCP_MAIN		24
+#define R8A78000_CPG_SGD1_VIO_DP_TX		25
+#define R8A78000_CPG_SGD2_VIO_DP_TX		26
+#define R8A78000_CPG_SGD4_VIO_DP_TX		27
+#define R8A78000_CPG_SGD8_VIO_DP_TX		28
+#define R8A78000_CPG_SGD16_VIO_DP_TX		29
+#define R8A78000_CPG_SGD1_VIO_DP_OTHER		30
+#define R8A78000_CPG_SGD2_VIO_DP_OTHER		31
+#define R8A78000_CPG_SGD4_VIO_DP_OTHER		32
+#define R8A78000_CPG_SGD8_VIO_DP_OTHER		33
+#define R8A78000_CPG_SGD16_VIO_DP_OTHER		34
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */

-- 
2.47.3