[PATCH v4 03/13] arm64: renesas: r8a78000: Add FCPV[BI] nodes

[Paul Elder]

Add DT nodes for the FCPVB and FCPVI IP cores in the R-Car X5H SoC.

Use the SGD1 clock as it is likely to be the clock used for data flow.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx>
Signed-off-by: Paul Elder <paul.elder+renesas@xxxxxxxxxxxxxxxx>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx>
Tested-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx>

---
Changes in v4:
- change clock from SGD4 to SGD1
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 72 +++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 437e49c58ff299a05411eb3aa50a0bb0d7fdda98..5caa9ab1c83a93a606c5191b71f5172158b0cc53 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -1574,6 +1574,78 @@ mdlc_aon: system-controller@c1338000 {
 			bootph-all;
 		};
 
+		fcpvi0: fcp@c5030000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5030000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD1_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x107>;
+			resets = <&mdlc_vio 0x107>;
+		};
+
+		fcpvi1: fcp@c5031000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5031000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD1_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x108>;
+			resets = <&mdlc_vio 0x108>;
+		};
+
+		fcpvi2: fcp@c5032000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5032000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD1_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x109>;
+			resets = <&mdlc_vio 0x109>;
+		};
+
+		fcpvi3: fcp@c5033000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5033000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD1_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x10a>;
+			resets = <&mdlc_vio 0x10a>;
+		};
+
+		fcpvb0: fcp@c5038000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5038000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD1_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x102>;
+			resets = <&mdlc_vio 0x102>;
+		};
+
+		fcpvb1: fcp@c5039000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5039000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD1_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x103>;
+			resets = <&mdlc_vio 0x103>;
+		};
+
+		fcpvb2: fcp@c503a000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc503a000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD1_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x104>;
+			resets = <&mdlc_vio 0x104>;
+		};
+
+		fcpvb3: fcp@c503b000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc503b000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD1_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x105>;
+			resets = <&mdlc_vio 0x105>;
+		};
+
+		fcpvb4: fcp@c503c000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc503c000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD1_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x106>;
+			resets = <&mdlc_vio 0x106>;
+		};
+
 		mdlc_cmnn: system-controller@ca410000 {
 			compatible = "renesas,r8a78000-mdlc";
 			reg = <0 0xca410000 0 0x1000>;

-- 
2.47.3