Pavel Machek wrote:
>
> Hi!
>
> > Assume you only have 2 pages of Physical memory (P0 and P1). Replacement policy is
> > LRU (Least Recently Used). No pages are in memory at the start, but P1 was LRU.
> > Show the Paging activity for a 32-bit word at offset 0x3fe in
> > both source and destination pages:
> >
> > T P0 P1
> > ------------------
> > 0 X X
> > 1 V0 X
> > 2 V0 V1 ;instruction loaded and decoded -- it stays in
> > the CPU now **
>
> CPU's don't work like that. Page fault means potentially
> context-switch, and there's _no_ place for information "where in the
> middle of instruction are we" in TSS.
>
> > 3 V2 V1 ;load first source page
> > 4 V2 V4 ;load first dest. page and copy 1st byte
> > 5 V2 V4 ;copy 2nd byte (pages are already in memory
> > 6 V3 V4 ;load 2nd source page
> > 7 V3 V5 ;load 2nd dest page and copy 3rd byte
> > 8 V3 V5 ;4th byte is copied.
>
> And they will not interrupt one mosvd operation like this!
--- In looking over my documentation on the PIII -- it appears you are right. All parts of a single instruction must be in memory before it can execute. All of the memory faults described can take place and the instruction is restarted at the beginning of the instruction each time. So you need a minimum of 6 RAM pages total to be available to user space programs for such unaligned moves. If alignment Checking is turned on, then user-space programs would be forced to have word moves and dword moves aligned properly. If that is the case, you would only need 4 total RAM pages for user-space (worst case). I don't know if Linux sets Alignment Check to 'on', but gcc does align for mX86, so you'd likely have to use assembler or non-portable C code.Regardless -- yup. You need at minimum 4 total pages of RAM for user space to execute that fragment. It still doesn't affect normal situation where there are megabytes (usually many) available for user program execution.
-l
-- Linda A Walsh | Trust Technology, Core Linux, SGI law@sgi.com | Voice: (650) 933-5338
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