Alan suggested to some poor hapless BP6 dual Celery owner that "noapic"
might help. For giggles, I used noapic on my HP SMP box where I've been
deprived of the extra processor for some time.
So here's my HP SMP box dmesg, booting with two processors for the first
time since 2.2.10. The "noapic" setting suggests that the APIC code needs a
little more debugging, or a HP braindeath compatibility checker, or since
I'm so unbelievably happy, just a note in Documentation somewhere saying
that HP XU 6/xxx SMP PPro's just need "noapic" to boot with both processors.
Also, it seems that my bogomips value more than doubled from what I expect
for two PPro 200's from ~ 400 to ~ 800. Not a biggie, but I'm sooooo happy.
:-) :-)
Scan SMP from c0000000 for 1024 bytes.
Scan SMP from c009fc00 for 1024 bytes.
Scan SMP from c00f0000 for 65536 bytes.
Intel MultiProcessor Specification v1.1
Virtual Wire compatibility mode.
OEM ID: HP Product ID: XX APIC at: 0xFEE00000
Processor #1 Pentium(tm) Pro APIC version 17
Floating point unit present.
Machine Exception supported.
64 bit compare & exchange supported.
Internal APIC present.
Bootup CPU
Processor #0 Pentium(tm) Pro APIC version 17
Floating point unit present.
Machine Exception supported.
64 bit compare & exchange supported.
Internal APIC present.
Bus #1 is ISA
Bus #0 is PCI
I/O APIC #16 Version 17 at 0xFEC00000.
Processors: 2
mapped APIC to ffffe000 (fee00000)
mapped IOAPIC to ffffd000 (fec00000)
Detected 199741468 Hz processor.
Console: colour VGA+ 80x25
Calibrating delay loop... 398.13 BogoMIPS
Memory: 94644k/98304k available (1480k kernel code, 420k reserved, 1340k
data, 8
0k init, 0k bigmem)
Dentry hash table entries: 16384 (order 5, 128k)
Buffer cache hash table entries: 131072 (order 7, 512k)
Page cache hash table entries: 32768 (order 5, 128k)
VFS: Diskquotas version dquot_6.4.0 initialized
Checking 386/387 coupling... OK, FPU using exception 16 error reporting.
Checking 'hlt' instruction... OK.
POSIX conformance testing by UNIFIX
mtrr: v1.35a (19990819) Richard Gooch (rgooch@atnf.csiro.au)
per-CPU timeslice cutoff: 50.18 usecs.
CPU1: Intel Pentium Pro stepping 09
Getting VERSION: 40011
Getting VERSION: 40011
Getting LVT0: 700
Getting LVT1: 400
setup_APIC_clock() called.
calibrating APIC timer ...
..... 1997313 CPU clocks in 1 timer chip tick.
..... 665768 APIC bus clocks in 1 timer chip tick.
..... CPU clock speed is 199.7313 MHz.
..... system bus clock speed is 66.5768 MHz.
CPU map: 3
Booting processor 0 eip 2000
Setting warm reset code and vector.
1.
2.
3.
Asserting INIT.
Deasserting INIT.
Sending STARTUP #1.
After apic_write.
Before start apic_write.
Startup point 1.
CPU#0 waiting for CALLOUT
Waiting for send to finish...
+Sending STARTUP #2.
After apic_write.
Before start apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Before Callout 0.
After Callout 0.
CALLIN, before enable_local_APIC().
setup_APIC_clock() called.
waiting for other CPU calibrating APIC ... done, continuing.
Calibrating delay loop... 398.95 BogoMIPS
Stack at about c5ffbfa4
OK.
CPU0: Intel Pentium Pro stepping 09
CPU has booted.
Before bogomips.
Total of 2 processors activated (797.08 BogoMIPS).
Before bogocount - setting activated=1.
Boot done.
checking TSC synchronization across CPUs: passed.
Setting commenced=1, go go go
Andrew van der Stock, Security Architect e-Secure Pty Ltd
"Secure in a Networked World" Phone: 02 9438 4984 Fax: 02 9438
4986
Suite 201, 2-4 Pacific Hwy, Mobile: 0412 532 963
St. Leonards NSW 2065 Australia http://www.e-Secure.com.au/
ACN 086 248 419
e-mail:A.vanderStock@e-Secure.com.au
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This archive was generated by hypermail 2b29 : Wed May 31 2000 - 21:00:24 EST