On Mon, May 22, 2000, Donald Becker <becker@scyld.com> wrote:
; On Mon, 22 May 2000, Dragan Stancevic wrote:
;
; assured that it would still with 66Mhz chips, and it insured that
; both memory and I/O operations would have a bus arbitration cycle.
You have a point here...
I understand the double role of the inw there
---Dragan
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