In another dimension, Vojtech Pavlik <vojtech@suse.cz> remarked:
>
> What I tried to say is that under normal operation, when every bit of
> hardware is in a good state, on an IDE transfer, that is, between
> harddrive electronics and ide controller, there shouldn't be bit errors.
So you're claiming the BER (bit error rate) should be zero? I know
of no transmission line that can achieve that. The best you can do
is reduce the BER to acceptable levels. Now I agree that the BER
should be very low on an IDE channel. I don't know how low.
Hopefully the spec makes some sort of assertion in that area.
To take the other fellow's example of 1 year, I calculate a required
BER of < 6E-17 in order to have a chance of not seeing a bit error
in one year at 66 MB/s. That's a pretty awesome BER if you can
achieve that.
In any event, I would expect other sources for noise to dominate at
such low BERs over such long periods of time. Voltage fluctuations
from the power supply due to perhaps switching transients on the AC
line (UPS cutting in, etc.), voltage coupling from adjacent
signaling lines or other nearby cables, someone holding a two-way
radio or cellphone close to the computer case (inducing a current in
the wires), or even a nearby flourescent light switching on (you'd
be surprised how much noise they make).
So, I would be very surprised not to see an occasional (hopefully
infrequent) bit error. It's always safest to assume there will be
one and have a plan for dealing with it. Set a threshold on an
acceptable CRC error rate, and use that as a guideline.
Just my two cents,
Dan Hopper
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This archive was generated by hypermail 2b29 : Mon Jul 31 2000 - 21:00:25 EST