Some followup -- it was setting/testing 1 integer. So it
seems it can safely be done w/o lock.
Talking with an internal engineer here -- NUMA uses MESI
cache control similarly to the i386 cache coherency model,
so a write of one CPU to a an area of memory will be seen
on other processors as soon as they ask for that memory.
Cache lines on the MIPS-NUMA use a 128-byte (not bit) cache line,
so for optimal performance, you'd want you weren't sharing
that cache line w/any other frequently used/modified data.
Now how to guarantee proper cache alignment on a given
platform....hmmm
-- Linda A Walsh | Trust Technology, Core Linux, SGI law@sgi.com | Voice: (650) 933-5338- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Mon Jul 31 2000 - 21:00:25 EST