Date: Mon, 28 Aug 2000 19:09:00 +0200 (CEST)
From: Andrea Arcangeli <andrea@suse.de>
On IA32 at least UnlockPage can't trigger the race because there's
the lock on the bus to do the clear_bit, but for example on the
alpha we do the clear bit with the load locked store conditional
operations (same thing on sparc64), thus we don't put any memory
barrier anymore between clearing the bit and reading the waitqueue.
This is not correct on sparc64, no younger loads can bypass the atomic
compare&swap operation. I bet the same is true for
load_locked+store_conditional on Alpha and MIPS. Did you check what
semantics Alpha guarentees in the reference manual (or more
importantly what the Alpha cpus really do)? I know you have a copy of
it and do read it Andrea ;-)))
I really cannot imagine a chip allowing the waitqueue_empty read to
occur before the ll/sc sequence, that would make no sense at all and
be very difficult silicon to even implement.
Later,
David S. Miller
davem@redhat.com
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Thu Aug 31 2000 - 21:00:22 EST