Hi all,
I am programming a device driver on PLX9060 chipset, and want to config DMA controller by IO memory,
but I find that can't access them in regular way,below are my codes.
>cat /proc/pci
Bus 0, device 16, function 0:
Bridge: PLX Unknown device (rev 3).
Vendor id=10b5. Device id=9060.
Medium devsel. Fast back-to-back capable. IRQ 12. Master Capable. Latency=64. Min Gnt=8.Max Lat=8.
Non-prefetchable 32 bit memory at 0xe7100000 [0xe7100000].
I/O at 0xe400 [0xe401].
Non-prefetchable 32 bit memory at 0xe7000000 [0xe7000000].
I want to access the virtual address of 0xe7000000 by ioremap()
struct dev {
u32 mem;
u32 io;
u32 space0;
...
};
mem = 0xe7100000;
io = 0xe400;
space0 = 0xe7000000;
ulong * remap = (ulong *)ioremap_nocache(space0, 0x200);
remap =remap + (0x100>>2);
/* check the return value of ioremap by printk()
* remap = 0xc2059100;
*/
/*
* Now test to see if I can access the DMA registers
* If I write -1 and get back 1FFF, then we accessed the
* DMA register, isn't it?
* there are two methods: remap[0x00] =x, writel(x, remap + 0x00), but I don't know their difference.
*/
remap[0x00] = 0xFFFFFFFF;
/* check the return value of remap by printk()
* remap[0x00] = 0xffffffff;
* remap[0x01] = 0xffffffff;
* remap[0x02] = 0xffffffff;
* remap[0x03] = 0xffffffff;
* remap[0x04] = 0xffffffff;
* remap[0x05] = 0xffffffff;
*/
then rerun the module
writel(0x03, remap + 0x00);
/* check the return value of remap by readl()
* remap + 0x00 = 0x00000003;
* remap + 0x01 = 0x00000003;
* remap + 0x02 = 0x00000003;
* remap + 0x03 = 0x00000003;
* remap + 0x04 = 0x00000003;
* remap + 0x05 = 0x00000003;
* remap + 0x06 = 0x00000003;
*/
so, I think probably access error,
I don't know how to update my code to access DMA registers.
any helps are appreciated.
thanks in advance.
-Jim
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