David S. Miller wrote:
> The I/O completion must flush the cache, not the VM subsystem.
>
> You must implement cache flushing at the DMA tranfer end point
> to fix the problem you are describing.
Thanks a lot. I understand now.
Aha, that's the reason why we have __flush_dcache_range() in ide_insw
for Sparc64 implementation, isn't it? I'll follow it for SuperH.
I'll close the entry for MM bugzilla, it's not MM bug.
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This archive was generated by hypermail 2b29 : Sat Jun 30 2001 - 21:00:18 EST